公开(公告)号：US09262558B2

公开(公告)日：2016-02-16

申请号：US13867154

申请日：2013-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., ltd.

Inventor： Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-kan Cheng

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  H01L27/02

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  G06F17/5081 ,  G06F2217/84 ,  H01L27/0207

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

公开(公告)号：US08732628B1

公开(公告)日：2014-05-20

申请号：US13742689

申请日：2013-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fan Wu ,  I-Fan Lin ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F1/38 ,  G03F7/70466

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract translation: 一种方法包括：在使用双重图案化技术（DPT）制造的集成电路（IC）的布局中选择电路图案的电路图案或网络。 所选择的电路图案或网络附近的电路图案被分组成一个或多个组。 对于每个组，对于两组不同的掩模分配，计算与掩模对准误差相关联的相应的预期电阻 - 电容（RC）提取误差成本。 一个或多个组中的电路图案被分配为通过相应的光掩模进行图案化，以便最小化预期RC提取误差成本的总和。

公开(公告)号：US09021412B2

公开(公告)日：2015-04-28

申请号：US14087065

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract translation: 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型使得能够利用一个或多个TSV对插入件进行精确的RC提取，从而提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US20140082578A1

公开(公告)日：2014-03-20

申请号：US14087065

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract translation: 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型能够使具有一个或多个TSV的插入件的精确RC提取，从而提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US08645877B2

公开(公告)日：2014-02-04

申请号：US13902102

申请日：2013-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/70

Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

Abstract translation: 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。