公开(公告)号：US20180330036A1

公开(公告)日：2018-11-15

申请号：US16046142

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

IPC: G06F17/50 ,  H01L21/768 ,  G01R31/28

CPC classification number: G06F17/5072 ,  G01R31/2858 ,  G06F17/5036 ,  G06F17/5081 ,  H01L21/768

Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

公开(公告)号：US10042967B2

公开(公告)日：2018-08-07

申请号：US15271301

申请日：2016-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

IPC: G06F17/00 ,  G06F17/50 ,  H01L21/768 ,  G01R31/28

Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present. The use of separate actual temperatures for components on different electrical networks mitigates false EM violations, thereby reducing loss of design overhead.

公开(公告)号：US20140082578A1

公开(公告)日：2014-03-20

申请号：US14087065

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract translation: 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型能够使具有一个或多个TSV的插入件的精确RC提取，从而提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US10719652B2

公开(公告)日：2020-07-21

申请号：US16460063

申请日：2019-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

IPC: G06F30/392 ,  H01L21/768 ,  G06F30/367 ,  G06F30/398 ,  G01R31/28

Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

公开(公告)号：US20200050735A1

公开(公告)日：2020-02-13

申请号：US16659134

申请日：2019-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen LIN ,  Ching-Shun Yang ,  Hsien Yu-Tseng

IPC: G06F17/50

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

公开(公告)号：US11055470B2

公开(公告)日：2021-07-06

申请号：US16659134

申请日：2019-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Ching-Shun Yang ,  Hsien Yu-Tseng

IPC: G06F30/398

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

公开(公告)号：US20170141003A1

公开(公告)日：2017-05-18

申请号：US15271301

申请日：2016-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

IPC: H01L21/66 ,  G01R31/28 ,  G06F17/50 ,  H01L21/768

CPC classification number: G06F17/5072 ,  G01R31/2858 ,  G06F17/5036 ,  G06F17/5081 ,  H01L21/768

Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present. The use of separate actual temperatures for components on different electrical networks mitigates false EM violations, thereby reducing loss of design overhead.

公开(公告)号：US09021412B2

公开(公告)日：2015-04-28

申请号：US14087065

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract translation: 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型使得能够利用一个或多个TSV对插入件进行精确的RC提取，从而提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US10509882B2

公开(公告)日：2019-12-17

申请号：US15334918

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Wan-Ru Lin ,  Ching-Shun Yang

IPC: G06F17/50

Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.

公开(公告)号：US20180046744A1

公开(公告)日：2018-02-15

申请号：US15334918

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Wan-Ru Lin ,  Ching-Shun Yang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.