公开(公告)号：US11094541B2

公开(公告)日：2021-08-17

申请号：US16934270

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chung Su ,  Ching-Yu Chang

IPC: H01L29/08 ,  H01L21/027 ,  H01L21/02 ,  G03F7/09

Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.

公开(公告)号：US20200350155A1

公开(公告)日：2020-11-05

申请号：US16934270

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chung Su ,  Ching-Yu Chang

IPC: H01L21/027 ,  H01L21/02 ,  G03F7/09

Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.

公开(公告)号：US09281192B2

公开(公告)日：2016-03-08

申请号：US14276168

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kao-Feng Liao ,  Yu-Ting Yen ,  Yu-Chung Su

IPC: H01L21/302 ,  H01L21/027 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

Abstract translation: IC器件制造工艺实现了最初在衬底上高度变化的材料的平面凹陷。 该方法包括形成聚合物涂层，CMP以形成平面表面，然后进行等离子体蚀刻，以实现聚合物涂层的平面凹陷。 该材料可以与聚合物涂层一起凹陷在一起，或随后与凹陷的聚合物涂层一起提供掩模。 任何高于一定高度的材料都被去除。 可以保护基本上低于该特定高度的结构免受污染并保持不变。 聚合物可以是光致抗蚀剂。 聚合物可以通过两步烘烤工艺和通过从基底下方排出烘烤室而为CMP工艺提供合适的粘附和均匀性。

公开(公告)号：US20150262812A1

公开(公告)日：2015-09-17

申请号：US14276168

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kao-Feng Liao ,  Yu-Ting Yen ,  Yu-Chung Su

IPC: H01L21/027 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

Abstract translation: IC器件制造工艺实现了最初在衬底上高度变化的材料的平面凹陷。 该方法包括形成聚合物涂层，CMP以形成平面表面，然后进行等离子体蚀刻，以实现聚合物涂层的平面凹陷。 该材料可以与聚合物涂层一起凹陷在一起，或随后与凹陷的聚合物涂层一起提供掩模。 任何高于一定高度的材料都被去除。 可以保护基本上低于该特定高度的结构免受污染并保持不变。 聚合物可以是光致抗蚀剂。 聚合物可以通过两步烘烤工艺和通过从基底下方排出烘烤室而为CMP工艺提供合适的粘附和均匀性。

公开(公告)号：US10770293B2

公开(公告)日：2020-09-08

申请号：US16105934

申请日：2018-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chung Su ,  Yahru Cheng ,  Ching-Yu Chang

IPC: H01L21/027 ,  G03F7/16 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: In a method of manufacturing a semiconductor device, a photo resist layer is formed over a substrate with underlying structures. The first photo resist layer is exposed to exposure radiation. The exposed first photo resist layer is developed with a developing solution. A planarization layer is formed over the developed photo resist layer. The underlying structures include concave portions, and a part of the concave portions is not filled by the developed first photo resist.

公开(公告)号：US10768527B2

公开(公告)日：2020-09-08

申请号：US16102429

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chung Su ,  Kuan-Hsin Lo ,  Yahru Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/16 ,  G03F7/20 ,  G03F7/09 ,  H01L21/027

Abstract: A method includes providing a photoresist solution that includes a first solvent having a first volume and a second solvent having a second volume, where the first solvent is different from the second solvent and where the first volume is less than the second volume; dispersing the photoresist solution over a substrate to form a film, where the dispersing evaporates a portion of the first solvent and a portion of the second solvent such that a remaining portion of the first solvent is greater than a remaining portion of the second solvent; baking the film; after baking the film, exposing the film to form an exposed film; and developing the exposed film.

公开(公告)号：US20200050110A1

公开(公告)日：2020-02-13

申请号：US16102429

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chung Su ,  Kuan-Hsin Lo ,  Yahru Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/16 ,  H01L21/027 ,  G03F7/09 ,  G03F7/20

Abstract: A method includes providing a photoresist solution that includes a first solvent having a first volume and a second solvent having a second volume, where the first solvent is different from the second solvent and where the first volume is less than the second volume; dispersing the photoresist solution over a substrate to form a film, where the dispersing evaporates a portion of the first solvent and a portion of the second solvent such that a remaining portion of the first solvent is greater than a remaining portion of the second solvent; baking the film; after baking the film, exposing the film to form an exposed film; and developing the exposed film.

公开(公告)号：US11120995B2

公开(公告)日：2021-09-14

申请号：US16700889

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Wei Hsu ,  Yu-Chung Su ,  Chen-Hao Wu ,  Shen-Nan Lee ,  Tsung-Ling Tsai ,  Teng-Chun Tsai

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/3105

Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.