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公开(公告)号:US20220344486A1
公开(公告)日:2022-10-27
申请号:US17238968
申请日:2021-04-23
发明人: Po-Chin CHANG , Ming-Huan Tsai , Li-Te Lin , Pinyen Lin
摘要: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.
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公开(公告)号:US20220319917A1
公开(公告)日:2022-10-06
申请号:US17845891
申请日:2022-06-21
发明人: Hung-Chang SUN , Po-Chin CHANG , Akira MINEJI , Zi-Wei FANG , Pinyen LIN
IPC分类号: H01L21/768 , H01L27/088 , H01L21/8234 , H01L23/535 , H01L23/532
摘要: A method for forming a semiconductor structure includes forming a gate structure on a substrate; depositing a first dielectric layer over the gate structure; depositing a second dielectric layer over the first dielectric layer and having a different density than the first dielectric layer; performing a first etching process on the first and second dielectric layers to form a trench; performing a second etching process on the first and second dielectric layers to modify the trench; filling a conductive material in the modified trench.
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公开(公告)号:US20190164820A1
公开(公告)日:2019-05-30
申请号:US15860565
申请日:2018-01-02
发明人: Hung-Chang SUN , Po-Chin CHANG , Akira MINEJI , Zi-Wei FANG , Pinyen LIN
IPC分类号: H01L21/768 , H01L21/8234 , H01L23/535 , H01L23/532 , H01L27/088
摘要: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A MEOL structure is formed on an etch stop layer. A patterned masking layer with at least one opening is formed on the MEOL structure and a first etching process is performed to form a trench in the MEOL structure. A second etching process is performed to modify at least one sidewall of the trench.
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公开(公告)号:US20220384268A1
公开(公告)日:2022-12-01
申请号:US17885410
申请日:2022-08-10
发明人: Po-Chin CHANG , Li-Te LIN , Pinyen LIN
IPC分类号: H01L21/8234 , H01L21/02 , H01L21/768 , H01L29/78 , H01L23/522 , H01L21/3213
摘要: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.
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公开(公告)号:US20200043795A1
公开(公告)日:2020-02-06
申请号:US16285052
申请日:2019-02-25
发明人: Po-Chin CHANG , Li-Te LIN , Pinyen LIN
IPC分类号: H01L21/8234 , H01L21/02 , H01L21/3213 , H01L29/78 , H01L23/522 , H01L21/768
摘要: A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.
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公开(公告)号:US20200006085A1
公开(公告)日:2020-01-02
申请号:US16383539
申请日:2019-04-12
发明人: Ya-Wen YEH , Yu-Tien SHEN , Shih-Chun HUANG , Po-Chin CHANG , Wei-Liang LIN , Yung-Sung YEN , Wei-Hao WU , Li-Te LIN , Pinyen LIN , Ru-Gun LIU
IPC分类号: H01L21/3213 , H01L21/66
摘要: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
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公开(公告)号:US20200294851A1
公开(公告)日:2020-09-17
申请号:US16888929
申请日:2020-06-01
发明人: Hung-Chang SUN , Po-Chin CHANG , Akira MINEJI , Zi-Wei FANG , Pinyen LIN
IPC分类号: H01L21/768 , H01L27/088 , H01L21/8234 , H01L23/535 , H01L23/532
摘要: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.
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公开(公告)号:US20240274471A1
公开(公告)日:2024-08-15
申请号:US18626229
申请日:2024-04-03
发明人: Po-Chin CHANG , Li-Te LIN , Pinyen LIN
IPC分类号: H01L21/8234 , H01L21/02 , H01L21/3213 , H01L21/768 , H01L23/522 , H01L29/78
CPC分类号: H01L21/823431 , H01L21/02263 , H01L21/3213 , H01L21/76802 , H01L21/823475 , H01L23/5226 , H01L29/7851
摘要: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact, and a first conductive via. The gate structure is over the semiconductor substrate. The source/drain region is adjacent the gate structure. The source/drain contact is over the source/drain region. The first conductive via is over the source/drain contact. From a top view, the first conductive via has two opposite first long sides and two opposite first short sides connecting the first long sides, and the first short sides are shorter than the first long sides and more curved than the first long sides. From a cross-sectional view, the first long sides of the first conductive via have bottom segments higher than a top surface of the gate structure.
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公开(公告)号:US20210013103A1
公开(公告)日:2021-01-14
申请号:US17033256
申请日:2020-09-25
发明人: Po-Chin CHANG , Li-Te LIN , Pinyen LIN
IPC分类号: H01L21/8234 , H01L21/02 , H01L21/768 , H01L29/78 , H01L23/522 , H01L21/3213
摘要: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.
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公开(公告)号:US20200335340A1
公开(公告)日:2020-10-22
申请号:US16921032
申请日:2020-07-06
发明人: Shih-Chun HUANG , Chiu-Hsiang CHEN , Ya-Wen YEH , Yu-Tien SHEN , Po-Chin CHANG , Chien Wen LAI , Wei-Liang LIN , Ya Hui CHANG , Yung-Sung YEN , Li-Te LIN , Pinyen LIN , Ru-Gun LIU , Chin-Hsiang LIN
IPC分类号: H01L21/033 , H01L21/027 , H01L21/311 , H01L21/02 , H01L21/265
摘要: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
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