公开(公告)号：US20230420438A1

公开(公告)日：2023-12-28

申请号：US17849300

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Chung YANG ,  Li-Hsien HUANG ,  Ming-Feng WU ,  Yao-Chun CHUANG ,  Jun HE

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L2224/29099 ,  H01L24/05 ,  H01L23/49827 ,  H01L23/3128 ,  H01L24/73 ,  H01L24/27 ,  H01L24/32 ,  H01L24/29 ,  H01L2224/16145 ,  H01L2224/0401 ,  H01L2224/05582 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/2761 ,  H01L2224/32225 ,  H01L24/16

Abstract: The present disclosure describes a structure that joins semiconductor packages and a method for forming the structure. The structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.

公开(公告)号：US20230178475A1

公开(公告)日：2023-06-08

申请号：US17832489

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun HE ,  Li-Hsien Huang ,  Yao-Chun Chuang ,  Chih-Lin Wang ,  Shih-Kang Tien

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L21/823475 ,  H01L21/823431 ,  H01L25/105

Abstract: A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third lane region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.

公开(公告)号：US20230402384A1

公开(公告)日：2023-12-14

申请号：US17835924

申请日：2022-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Hong LIN ,  Yinlung LU ,  Jun HE ,  Hsuan-Ming HUANG ,  Hsin-Chun CHANG

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53276 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76849 ,  H01L23/5226

Abstract: Material properties of graphene can be leveraged to improve performance of interconnects in an integrated circuit. One way to circumvent challenges involved in depositing graphene onto a copper surface is to incorporate graphene into the bulk metal layer to create a hybrid metal/graphene interconnect structure. Such a hybrid structure can be created instead of, or in addition to, forming a graphene film on the metal surface as a metal capping layer. A first method for embedding graphene into a copper damascene layer is to alternate the metal fill process with graphene deposition to create a composite graphene matrix. A second method is to implant carbon atoms into a surface layer of metal. A third method is to disperse graphene flakes in a damascene copper plating solution to create a distributed graphene matrix. Any combination of these methods can be used to enhance conductivity of the interconnect.

公开(公告)号：US20230402385A1

公开(公告)日：2023-12-14

申请号：US17837664

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Hong LIN ,  Yinlung LU ,  Jun HE ,  An Shun TENG ,  Chun-Wei CHANG

IPC: H01L23/532 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/823475 ,  H01L27/088 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L21/76843 ,  H01L21/76816 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/53276

Abstract: A graphene-clad metal interconnect extends material properties of graphene to both damascene and patterned interconnect structures at lower metal layers, leading to significant reductions in resistance. Graphene cladding can be used with or without a metal barrier/liner. Presence of a barrier/liner can serve to catalyze growth of an overlying graphene layer. Graphene may also be selectively grown on barrier surfaces. Fully integrated structures and process flows for integrated circuits with graphene-clad metallization are described.

公开(公告)号：US20230170258A1

公开(公告)日：2023-06-01

申请号：US17833613

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien HUANG ,  Yao-Chun CHUANG ,  Hua-Wei TSENG ,  Yu-Jin HU ,  Jun HE

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L24/94 ,  H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214

Abstract: An integrated circuit chip package and a method of fabricating the same are disclosed. The method includes forming a device layer on a substrate with a first die and a second die, forming an interconnect structure on the device layer, depositing an insulating layer on the interconnect structure, forming first and second conductive pads on the interconnect structure, forming first and second conductive vias on the first and second conductive pads, respectively, patterning a polymer layer to form first and second buffer layers with tapered side profiles on the first and second conductive vias, respectively, forming a trench in the substrate and between the first and second buffer layers, and dicing the substrate through the trench to separate the first die from the second die. Portions of the first and second conductive pads extend over the insulating layer.