公开(公告)号：US20230170258A1

公开(公告)日：2023-06-01

申请号：US17833613

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien HUANG ,  Yao-Chun CHUANG ,  Hua-Wei TSENG ,  Yu-Jin HU ,  Jun HE

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L24/94 ,  H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214

Abstract: An integrated circuit chip package and a method of fabricating the same are disclosed. The method includes forming a device layer on a substrate with a first die and a second die, forming an interconnect structure on the device layer, depositing an insulating layer on the interconnect structure, forming first and second conductive pads on the interconnect structure, forming first and second conductive vias on the first and second conductive pads, respectively, patterning a polymer layer to form first and second buffer layers with tapered side profiles on the first and second conductive vias, respectively, forming a trench in the substrate and between the first and second buffer layers, and dicing the substrate through the trench to separate the first die from the second die. Portions of the first and second conductive pads extend over the insulating layer.