知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.016 seconds)

    INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF
    1.
    发明申请
    INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF 有权

    公开(公告)号：US20220216165A1

    公开(公告)日：2022-07-07

    申请号：US17706039

    申请日：2022-03-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jian-Hong LIN ,  Kuo-Yen LIU ,  Hsin-Chun CHANG ,  Tzu-Li LEE ,  Yu-Ching LEE ,  Yih-Ching WANG

    IPC: H01L23/00 ,  H01L23/58 ,  H01L27/02 ,  H01L23/522

    Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

    Through-Circuit Vias In Interconnect Structures
    4.
    发明公开
    Through-Circuit Vias In Interconnect Structures 审中-公开

    公开(公告)号：US20230386973A1

    公开(公告)日：2023-11-30

    申请号：US18232200

    申请日：2023-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Hong LIN ,  Hsin-Chun CHANG ,  Ming-Hong HSIEH ,  Ming-Yih WANG ,  Yinlung LU

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/481 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/5283

    Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

    GRAPHENE-METAL HYBRID INTERCONNECT
    8.
    发明公开
    GRAPHENE-METAL HYBRID INTERCONNECT 审中-公开

    公开(公告)号：US20230402384A1

    公开(公告)日：2023-12-14

    申请号：US17835924

    申请日：2022-06-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Hong LIN ,  Yinlung LU ,  Jun HE ,  Hsuan-Ming HUANG ,  Hsin-Chun CHANG

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53276 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76849 ,  H01L23/5226

    Abstract: Material properties of graphene can be leveraged to improve performance of interconnects in an integrated circuit. One way to circumvent challenges involved in depositing graphene onto a copper surface is to incorporate graphene into the bulk metal layer to create a hybrid metal/graphene interconnect structure. Such a hybrid structure can be created instead of, or in addition to, forming a graphene film on the metal surface as a metal capping layer. A first method for embedding graphene into a copper damascene layer is to alternate the metal fill process with graphene deposition to create a composite graphene matrix. A second method is to implant carbon atoms into a surface layer of metal. A third method is to disperse graphene flakes in a damascene copper plating solution to create a distributed graphene matrix. Any combination of these methods can be used to enhance conductivity of the interconnect.

    ONE-TIME PROGRAMMABLE MEMORY DEVICE INCLUDING ANTI-FUSE ELEMENT
    9.
    发明公开
    ONE-TIME PROGRAMMABLE MEMORY DEVICE INCLUDING ANTI-FUSE ELEMENT 审中-公开

    公开(公告)号：US20230284442A1

    公开(公告)日：2023-09-07

    申请号：US18304834

    申请日：2023-04-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chiung-Ting OU ,  Ming-Yih WANG ,  Jian-Hong LIN

    IPC: H10B20/20 ,  H01L23/48

    CPC classification number: H10B20/20 ,  H01L23/481

    Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.

    Through-Circuit Vias in Interconnect Structures
    10.
    发明申请
    Through-Circuit Vias in Interconnect Structures 有权

    公开(公告)号：US20210375723A1

    公开(公告)日：2021-12-02

    申请号：US17162584

    申请日：2021-01-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Hong LIN ,  Hsin-Chun CHANG ,  Ming-Hong HSIEH ,  Ming-Yih WANG ,  Yinlung LU

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Patent Agency Ranking