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公开(公告)号：US11329101B2
公开(公告)日：2022-05-10
申请号：US17094008
申请日：2020-11-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jack Liu , Charles Chew-Yuen Young
Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.
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公开(公告)号：US11195879B2
公开(公告)日：2021-12-07
申请号：US17093980
申请日：2020-11-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jack Liu , Charles Chew-Yuen Young
Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.
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公开(公告)号：US20180151221A1
公开(公告)日：2018-05-31
申请号：US15840803
申请日：2017-12-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsin-Cheng Chen , Jack Liu
IPC: G11C11/419 , G11C11/418 , G11C13/04
CPC classification number: G11C11/419 , G11C7/103 , G11C11/418 , G11C13/048
Abstract: A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
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公开(公告)号：US09727683B2
公开(公告)日：2017-08-08
申请号：US14985100
申请日：2015-12-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jack Liu
IPC: H01L23/52 , G06F17/50 , H01L23/528 , H01L23/522
CPC classification number: G06F17/5077 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L28/00
Abstract: An integrated circuit includes a cell and a first plurality of conductive segments. Each of the first plurality of conductive segments has a first predetermined width, and the first plurality of conductive segments includes a first conductive segment, and a second conductive segment. The first conductive segment and the second conductive segment are coupled to the cell to transmit a signal, and a distance between the first conductive segment and the second conductive segment is greater than the first predetermined width.
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5.发明授权公开(公告)号：US11176983B2
公开(公告)日：2021-11-16
申请号：US17102716
申请日：2020-11-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jack Liu , Charles Chew-Yuen Young
Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.
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Patent Agency Ranking
公开(公告)号：US11163933B2
公开(公告)日：2021-11-02
申请号：US16858400
申请日：2020-04-24
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jack Liu
IPC: G06F30/394 , G06F30/392 , H01L23/522 , H01L23/528
Abstract: A method that includes operations below and at least one of the operations is performed by a processor. Whether at least one condition is present in a signal to be received or transmitted by a terminal of a cell of an integrated circuit is determined. When the at least one condition is present in the signal, a plurality of conductive segments of the integrated circuit is assigned, to transmit the signal to the terminal of the cell. Each conductive segment of a first set of conductive segments of the plurality of conductive segments has a first predetermined width, and a distance between adjacent two conductive segments of the first set of conductive segments is greater than the first predetermined width.
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公开(公告)号：US10944007B2
公开(公告)日：2021-03-09
申请号：US16578301
申请日：2019-09-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jack Liu , Charles Chew-Yuen Young
IPC: H01L29/786 , H01L27/12 , H01L29/40 , H01L27/092 , H01L23/535 , H01L21/84 , H01L21/8238 , H01L29/06
Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.
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公开(公告)号：US20210057486A1
公开(公告)日：2021-02-25
申请号：US17094008
申请日：2020-11-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jack Liu , Charles Chew-Yuen Young
Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.
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公开(公告)号：US20200350005A1
公开(公告)日：2020-11-05
申请号：US16933499
申请日：2020-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsin-Cheng CHEN , Jack Liu
IPC: G11C11/419 , G11C11/418 , G11C7/10
Abstract: A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
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公开(公告)号：US20190371943A1
公开(公告)日：2019-12-05
申请号：US15992766
申请日：2018-05-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jack Liu , Charles Chew-Yuen Young
IPC: H01L29/786 , H01L27/12 , H01L29/40 , H01L29/06 , H01L23/535 , H01L21/84 , H01L21/8238 , H01L27/092
Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.
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