公开(公告)号：US11120999B2

公开(公告)日：2021-09-14

申请号：US16770084

申请日：2018-12-11

Applicant: TOKYO ELECTRON LIMITED ,  UNIVERSITE D'ORLEANS

Inventor： Koichi Yatsuda ,  Kaoru Maekawa ,  Nagisa Sato ,  Kumiko Ono ,  Shigeru Tahara ,  Jacques Faguet ,  Remi Dussart ,  Thomas Tillocher ,  Philippe Lefaucheux ,  Gaëlle Antoun

IPC: H01L21/311 ,  H01L21/3065 ,  H01J37/32

Abstract: A plasma etching method includes a physisorption step for causing an adsorbate that is based on first processing gas to be physisorbed onto a film to be etched, while cooling an object to be processed on which the film to be etched is provided; and an etching step for etching the film to be etched by causing the adsorbate to react with the film to be etched, using the plasma of second processing gas.

公开(公告)号：US10593556B2

公开(公告)日：2020-03-17

申请号：US15654307

申请日：2017-07-19

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koichi Yatsuda ,  Takashi Hayakawa ,  Hiroshi Okuno ,  Reiji Niino ,  Hiroyuki Hashimoto ,  Tatsuya Yamaguchi

IPC: H01L21/311 ,  H01L21/67 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

Abstract: There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a polymer having a urea bond by supplying polymerizing raw materials to a surface of the substrate on which an etching target film formed; forming an etching pattern on the masking film; subsequently, etching the etching target film with a processing gas using the etching pattern; and subsequently, removing the masking film by heating the substrate to depolymerize the polymer.

公开(公告)号：US20190157083A1

公开(公告)日：2019-05-23

申请号：US16253380

申请日：2019-01-22

Applicant: Tokyo Electron Limited

Inventor： Mitsuaki Iwashita ,  Takeshi Nagao ,  Nobutaka Mizutani ,  Takashi Tanaka ,  Koichi Yatsuda ,  Kazutoshi Iwai ,  Yuichiro Inatomi

IPC: H01L21/033 ,  C23C14/04 ,  C23C18/16 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/311 ,  C23C18/50 ,  C23C18/32 ,  C23C18/18 ,  C23C16/04

Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.

公开(公告)号：US10910259B2

公开(公告)日：2021-02-02

申请号：US16213119

申请日：2018-12-07

Applicant: TOKYO ELECTRON LIMITED ,  IMEC VZW

Inventor： Koichi Yatsuda ,  Tatsuya Yamaguchi ,  Yannick Feurprier ,  Frederic Lazzarino ,  Jean-Francois de Marneffe ,  Khashayar Babaei Gavan

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105

Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

公开(公告)号：US10325780B2

公开(公告)日：2019-06-18

申请号：US15831831

申请日：2017-12-05

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koichi Yatsuda ,  Takashi Hayakawa ,  Tatsuya Yamaguchi

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: There is provided a method of manufacturing a semiconductor device, which includes: supplying a raw material for polymerization to a porous low dielectric constant film formed on a substrate for manufacturing a semiconductor device, and filling holes formed in the porous low dielectric constant film with a polymer having a urea bond; subsequently, forming a pattern mask for etching on a surface of the porous low dielectric constant film; subsequently, etching the porous low dielectric constant film; subsequently, removing the pattern mask; and heating the substrate to depolymerize the polymer.

公开(公告)号：US11495490B2

公开(公告)日：2022-11-08

申请号：US17137945

申请日：2020-12-30

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koichi Yatsuda ,  Tatsuya Yamaguchi ,  Yannick Feurprier ,  Frederic Lazzarino ,  Jean-Francois de Marneffe ,  Khashayar Babaei Gavan

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105

Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

公开(公告)号：US11171050B2

公开(公告)日：2021-11-09

申请号：US16491678

申请日：2018-02-27

Applicant: Tokyo Electron Limited

Inventor： Koichi Yatsuda ,  Takashi Hayakawa ,  Mitsuaki Iwashita ,  Takashi Tanaka

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method includes a step of performing a selective catalyst treatment by supplying a catalyst solution to an upper surface of an exposed interconnection layer forming a step portion of a stepped shape formed by pair layers stacked to form the stepped shape, the pair layer including an interconnection layer formed on an insulating layer, and a step of selectively growing a metal layer by performing electroless plating on the upper surface of the interconnection layer on which the catalyst treatment is performed.

公开(公告)号：US11004684B2

公开(公告)日：2021-05-11

申请号：US16253380

申请日：2019-01-22

Applicant: Tokyo Electron Limited

Inventor： Mitsuaki Iwashita ,  Takeshi Nagao ,  Nobutaka Mizutani ,  Takashi Tanaka ,  Koichi Yatsuda ,  Kazutoshi Iwai ,  Yuichiro Inatomi

IPC: H01L21/033 ,  H01L21/308 ,  C23C18/16 ,  C23C16/04 ,  C23C14/04 ,  C23C18/18 ,  C23C18/32 ,  C23C18/50 ,  H01L21/311 ,  H01L21/3213

Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.

公开(公告)号：US10224202B2

公开(公告)日：2019-03-05

申请号：US15473810

申请日：2017-03-30

Applicant: Tokyo Electron Limited

Inventor： Mitsuaki Iwashita ,  Takeshi Nagao ,  Nobutaka Mizutani ,  Takashi Tanaka ,  Koichi Yatsuda ,  Kazutoshi Iwai ,  Yuichiro Inatomi

IPC: H01L21/033 ,  H01L21/308 ,  C23C18/16 ,  C23C16/04 ,  C23C14/04

Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.

公开(公告)号：US20180158693A1

公开(公告)日：2018-06-07

申请号：US15831831

申请日：2017-12-05

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koichi Yatsuda ,  Takashi Hayakawa ,  Tatsuya Yamaguchi

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/02282 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76832 ,  H01L23/5329

Abstract: There is provided a method of manufacturing a semiconductor device, which includes: supplying a raw material for polymerization to a porous low dielectric constant film formed on a substrate for manufacturing a semiconductor device, and filling holes formed in the porous low dielectric constant film with a polymer having a urea bond; subsequently, forming a pattern mask for etching on a surface of the porous low dielectric constant film; subsequently, etching the porous low dielectric constant film; subsequently, removing the pattern mask; and heating the substrate to depolymerize the polymer.