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公开(公告)号：US10446537B2
公开(公告)日：2019-10-15
申请号：US15835396
申请日：2017-12-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Gianluca Boselli , Muhammad Yusuf Ali
Abstract: In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.
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公开(公告)号：US10396199B2
公开(公告)日：2019-08-27
申请号：US15624741
申请日：2017-06-16
Applicant: Texas Instruments Incorporated
Inventor： Aravind C. Appaswamy , Akram A. Salman , Farzan Farbiz , Gianluca Boselli
Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
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公开(公告)号：US09633991B2
公开(公告)日：2017-04-25
申请号：US14949417
申请日：2015-11-23
Applicant: Texas Instruments Incorporated
Inventor： Akram A. Salman , Farzan Farbiz , Ann Margaret Concannon , Gianluca Boselli
CPC classification number: H01L27/0262 , H01L27/0248 , H01L27/0259 , H01L27/0266 , H02H9/046
Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
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公开(公告)号：US20160086936A1
公开(公告)日：2016-03-24
申请号：US14949417
申请日：2015-11-23
Applicant: Texas Instruments Incorporated
Inventor： Akram A. Salman , Farzan Farbiz , Ann Margaret Concannon , Gianluca Boselli
CPC classification number: H01L27/0262 , H01L27/0248 , H01L27/0259 , H01L27/0266 , H02H9/046
Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
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公开(公告)号：US20170288058A1
公开(公告)日：2017-10-05
申请号：US15624741
申请日：2017-06-16
Applicant: Texas Instruments Incorporated
Inventor： Aravind C. Appaswamy , Akram A. Salman , Farzan Farbiz , Gianluca Boselli
IPC: H01L29/78
CPC classification number: H01L29/7835 , H01L27/027 , H01L29/1087
Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
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Patent Agency Ranking
公开(公告)号：US09711643B2
公开(公告)日：2017-07-18
申请号：US14552257
申请日：2014-11-24
Applicant: Texas Instruments Incorporated
Inventor： Aravind C. Appaswamy , Akram A. Salman , Farzan Farbiz , Gianluca Boselli
CPC classification number: H01L29/7835 , H01L27/027 , H01L29/1087
Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
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公开(公告)号：US20160224716A1
公开(公告)日：2016-08-04
申请号：US14612071
申请日：2015-02-02
Applicant: Texas Instruments Incorporated
Inventor： Farzan Farbiz , Aravind C. Appaswamy , Akram A. Salman , Gianluca Boselli
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5063
Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.
Abstract translation: 设计二极管的方法包括产生二极管的布局并基于布局计算计算的电压过冲。 该计算包括计算变量：二极管的N区长度; ESD事件期间的电流密度; 电子电荷 空穴流动性 电子迁移率; 二极管的掺杂浓度; 和ESD事件的上升时间。
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公开(公告)号：US09224724B2
公开(公告)日：2015-12-29
申请号：US13901772
申请日：2013-05-24
Applicant: Texas Instruments Incorporated
Inventor： Akram A. Salman , Farzan Farbiz , Ann Margaret Concannon , Gianluca Boselli
IPC: H01L27/02
CPC classification number: H01L27/0262 , H01L27/0248 , H01L27/0259 , H01L27/0266 , H02H9/046
Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
Abstract translation: 集成电路包括具有多个平行开关支脚的双向ESD装置。 每个开关支路包括背对背配置中的第一电流开关和第二电流开关。 每个第一电流开关的第一电流供应节点耦合到ESD装置的第一端子。 每个第二电流开关的第二电流供应节点耦合到ESD装置的第二端子。 每个第一电流开关的第一电流采集节点耦合到相应的第二电流开关的第二电流采集节点。 每个第一当前交换机中的第一当前收集节点不耦合到任何其它第一当前收集节点，并且类似地，每个实例中的第二当前收集节点第二当前交换机不耦合到任何其它第二当前收集节点。
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公开(公告)号：US09629294B2
公开(公告)日：2017-04-18
申请号：US14101419
申请日：2013-12-10
Applicant: Texas Instruments Incorporated
Inventor： John Eric Kunz, Jr. , Jonathan Scott Brodsky , Gianluca Boselli
CPC classification number: H05K13/08 , G01R31/001 , H01L22/34 , H01L27/0292 , H01L2224/16245 , H01L2224/48247 , H01L2224/48465 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , Y10T29/49004 , H01L2924/00 , H01L2924/00014
Abstract: An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.
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公开(公告)号：US09418197B1
公开(公告)日：2016-08-16
申请号：US14612071
申请日：2015-02-02
Applicant: Texas Instruments Incorporated
Inventor： Farzan Farbiz , Aravind C. Appaswamy , Akram A. Salman , Gianluca Boselli
CPC classification number: G06F17/5081 , G06F17/5063
Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.
Abstract translation: 设计二极管的方法包括产生二极管的布局并基于布局计算计算的电压过冲。 该计算包括计算变量：二极管的N区长度; ESD事件期间的电流密度; 电子电荷 空穴流动性 电子迁移率; 二极管的掺杂浓度; 和ESD事件的上升时间。
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