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公开(公告)号：US20180247925A1
公开(公告)日：2018-08-30
申请号：US15445671
申请日：2017-02-28
Applicant: Texas Instruments Incorporated
Inventor： Akram A. Salman , Muhammad Yusuf Ali
IPC: H01L27/02 , H01L29/735 , H01L29/73 , H01L27/06 , H01L21/8222
CPC classification number: H01L27/0255 , H01L29/735
Abstract: Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.
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公开(公告)号：US11011508B2
公开(公告)日：2021-05-18
申请号：US16220881
申请日：2018-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.
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公开(公告)号：US20210028163A1
公开(公告)日：2021-01-28
申请号：US16518304
申请日：2019-07-22
Applicant: Texas Instruments Incorporated
Inventor： Xianzhi Dai , Muhammad Yusuf Ali
IPC: H01L27/02 , H01L21/768
Abstract: A semiconductor device has a protected node and a reference node, and a bi-directional ESD structure electrically coupled between the protected node and the reference node. The bi-directional ESD structure includes a main transistor electrically coupled between the protected node and the reference node, an upper control transistor with current nodes electrically coupled between the protected node and a control node of the main transistor, and a lower control transistor with current nodes electrically coupled between the reference node and a control node of the main transistor. The bi-directional ESD structure also includes an upper trigger network configured to provide a transient on-state signal to the upper control transistor from a positive electrical pulse on the protected node. The bi-directional ESD structure further includes a lower trigger network configured to provide a transient on-state signal to the lower control transistor from a negative electrical pulse on the protected node.
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公开(公告)号：US10373944B2
公开(公告)日：2019-08-06
申请号：US15445671
申请日：2017-02-28
Applicant: Texas Instruments Incorporated
Inventor： Akram A. Salman , Muhammad Yusuf Ali
IPC: H01L27/02 , H01L29/735
Abstract: Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.
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公开(公告)号：US09614368B2
公开(公告)日：2017-04-04
申请号：US14618825
申请日：2015-02-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Xianzhi Dai , Farzan Farbiz , Muhammad Yusuf Ali
IPC: H02H9/04
CPC classification number: H02H9/046 , H01L23/5286 , H01L27/0248 , H01L27/0629 , H01L27/092
Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.
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Patent Agency Ranking
公开(公告)号：US11152350B2
公开(公告)日：2021-10-19
申请号：US16220793
申请日：2018-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mahalingam Nandakumar , Alan Erik Segervall , Muhammad Yusuf Ali
IPC: H01L27/02 , H01L27/06 , H01L29/06 , H01L27/08 , H01L27/092 , H01L21/266
Abstract: An electronic device, e.g. integrated circuit, has an n-type region and a p-type region located within a semiconductor substrate, the n-type region and the p-type region each intersecting the substrate surface. A dielectric structure is located directly on the substrate surface. The dielectric structure has first and second laterally opposed sides, with the first side located over the n-type region and the second side located over the p-type region.
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公开(公告)号：US10998308B2
公开(公告)日：2021-05-04
申请号：US16518304
申请日：2019-07-22
Applicant: Texas Instruments Incorporated
Inventor： Xianzhi Dai , Muhammad Yusuf Ali
IPC: H01L27/02 , H01L21/76 , H01L21/768
Abstract: A semiconductor device has a protected node and a reference node, and a bi-directional ESD structure electrically coupled between the protected node and the reference node. The bi-directional ESD structure includes a main transistor electrically coupled between the protected node and the reference node, an upper control transistor with current nodes electrically coupled between the protected node and a control node of the main transistor, and a lower control transistor with current nodes electrically coupled between the reference node and a control node of the main transistor. The bi-directional ESD structure also includes an upper trigger network configured to provide a transient on-state signal to the upper control transistor from a positive electrical pulse on the protected node. The bi-directional ESD structure further includes a lower trigger network configured to provide a transient on-state signal to the lower control transistor from a negative electrical pulse on the protected node.
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公开(公告)号：US09154133B2
公开(公告)日：2015-10-06
申请号：US13630721
申请日：2012-09-28
Applicant: Texas Instruments Incorporated
Inventor： Muhammad Yusuf Ali , Rajkumar Sankaralingam , Charles M. Branch
IPC: H03H9/46 , H03K19/003 , H02H9/04 , H01L27/02
CPC classification number: H03K19/00384 , H01L27/0266 , H02H9/046
Abstract: An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.
Abstract translation: 逆变器型电平移位器包括第一电源电压和第一接地电压。 第一逆变器对第一电源电压和第一接地电压进行操作以产生第一逆变器输出。 第一反相器包括第一PMOS晶体管，其具有耦合到阻塞PMOS晶体管的源极的漏极和具有耦合到阻塞NMOS晶体管的源极的漏极的第一NMOS晶体管。 电平移位器还包括第二电源电压和第二接地电压，以及第二反相器，耦合到第一反相器输出并对第二电源电压和第二接地电压进行操作。 阻塞PMOS在第一电源电压的第二电源电压中的电压尖峰的事件上提供所需的阻塞，并且阻塞NMOS晶体管相对于第二电源电压在第二接地电压中的电压尖峰的事件上提供所需的阻塞 第一接地电压。
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公开(公告)号：US11133143B2
公开(公告)日：2021-09-28
申请号：US16585259
申请日：2019-09-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Masahiro Yoshioka , Muhammad Yusuf Ali , Kevin Ryan Duke
Abstract: A two-wire current loop system includes a current loop with a transmitter and a host. The system also includes a monolithic integrated circuit included with the transmitter. The monolithic integrated circuit includes: 1) a power supply terminal coupled to the current loop; 2) a loop ground terminal coupled to the current loop and configured to output a current to the current loop; 3) device circuitry with a power supply node and an internal ground node, wherein the power supply node is coupled to the power supply terminal; and 4) a reverse wiring protection circuit coupled between the internal ground node of the device circuitry and the loop ground terminal.
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公开(公告)号：US10446537B2
公开(公告)日：2019-10-15
申请号：US15835396
申请日：2017-12-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Gianluca Boselli , Muhammad Yusuf Ali
Abstract: In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.
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