公开(公告)号：US09496313B2

公开(公告)日：2016-11-15

申请号：US14292198

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/265 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 通过在CMOS晶体管之间和嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽，形成包含CMOS晶体管和嵌入式热电元件的集成电路。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

公开(公告)号：US20190296013A1

公开(公告)日：2019-09-26

申请号：US16424235

申请日：2019-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Fred Salzman ,  Bradley David Sucher

IPC: H01L27/092 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8238

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

公开(公告)号：US10438837B2

公开(公告)日：2019-10-08

申请号：US15991938

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bradley David Sucher ,  Bernard John Fischer ,  Abbas Ali

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm−2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

公开(公告)号：US10304721B1

公开(公告)日：2019-05-28

申请号：US15859447

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bradley David Sucher ,  Neil L. Gardner ,  Binghua Hu

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234

Abstract: In some examples, a method includes etching a substrate to form a trench, wherein the trench includes sidewalls. The method further includes forming a first isolation region in the trench by growing a first layer of a first thickness on the sidewalls using a dry oxidation technique and depositing a second layer to fill a portion of the trench, the second layer contacting the first layer. The method further includes etching third and fourth layers atop the substrate to expose a first portion of the substrate. The method further includes growing a second isolation region in the substrate through the first portion by using a dry-wet-dry oxidation technique.

公开(公告)号：US20180254272A1

公开(公告)日：2018-09-06

申请号：US15969296

申请日：2018-05-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Fred Salzman ,  Bradley David Sucher

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823892 ,  H01L27/0248 ,  H01L29/1083

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

公开(公告)号：US11056490B2

公开(公告)日：2021-07-06

申请号：US16424235

申请日：2019-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Fred Salzman ,  Bradley David Sucher

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/10

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

公开(公告)号：US10304827B2

公开(公告)日：2019-05-28

申请号：US15969296

申请日：2018-05-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Fred Salzman ,  Bradley David Sucher

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/02

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

公开(公告)号：US20180053764A1

公开(公告)日：2018-02-22

申请号：US15238445

申请日：2016-08-16

Applicant: Texas Instruments Incorporated

Inventor： James Fred Salzman ,  Bradley David Sucher

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823892 ,  H01L29/1083

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

公开(公告)号：US20170062518A1

公开(公告)日：2017-03-02

申请号：US15350694

申请日：2016-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L27/16 ,  H01L35/32 ,  H01L21/8238 ,  H01L21/265 ,  H01L35/04 ,  H01L35/34

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 在所述实施例中，通过在CMOS晶体管之间以及嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽来形成嵌入式热电元件。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

公开(公告)号：US10032663B1

公开(公告)日：2018-07-24

申请号：US15603856

申请日：2017-05-24

Applicant: Texas Instruments Incorporated

Inventor： Bradley David Sucher ,  Bernard John Fischer ,  Abbas Ali

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06

Abstract: A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench implanting using an angled implant then forms doped sidewalls of the trenches. Furnace annealing after trench implanting includes a ramp-up portion to a maximum peak temperature range of at least 975° C. and ramp-down portion, wherein the ramp-up portion is performed in a non-oxidizing ambient for at least a 100° C. temperature ramp portion with an O2 flow being less than 0.1 standard liter per minute (SLM). The sidewalls and a bottom of the trench are thermally oxidized to form a liner oxide after furnace annealing to form dielectric lined trenches. The dielectric lined trenches are filled with a fill material, and overburden portions of the fill material are then removed to form filled trenches.