公开(公告)号：US09691751B2

公开(公告)日：2017-06-27

申请号：US14570530

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Khanh Quang Le ,  Collin White ,  Sopa Chevacharoenkul ,  Ashley Norris ,  Bernard John Fischer

IPC: H01L27/02 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L27/0248 ,  H01L21/763 ,  H01L21/823878 ,  H01L29/0649

Abstract: A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) ≧5 and a trench depth ≧10 μm. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance ≦100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.

公开(公告)号：US10438837B2

公开(公告)日：2019-10-08

申请号：US15991938

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bradley David Sucher ,  Bernard John Fischer ,  Abbas Ali

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm−2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

公开(公告)号：US10032663B1

公开(公告)日：2018-07-24

申请号：US15603856

申请日：2017-05-24

Applicant: Texas Instruments Incorporated

Inventor： Bradley David Sucher ,  Bernard John Fischer ,  Abbas Ali

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06

Abstract: A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench implanting using an angled implant then forms doped sidewalls of the trenches. Furnace annealing after trench implanting includes a ramp-up portion to a maximum peak temperature range of at least 975° C. and ramp-down portion, wherein the ramp-up portion is performed in a non-oxidizing ambient for at least a 100° C. temperature ramp portion with an O2 flow being less than 0.1 standard liter per minute (SLM). The sidewalls and a bottom of the trench are thermally oxidized to form a liner oxide after furnace annealing to form dielectric lined trenches. The dielectric lined trenches are filled with a fill material, and overburden portions of the fill material are then removed to form filled trenches.