公开(公告)号：US10574246B2

公开(公告)日：2020-02-25

申请号：US15949294

申请日：2018-04-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara Gunturi ,  Sundarrajan Rangachari ,  Aswath Vs ,  Raunak Dhaniwala

IPC: H03L7/24 ,  H03K21/38 ,  H03L7/02

Abstract: A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.

公开(公告)号：US20220271762A1

公开(公告)日：2022-08-25

申请号：US17488559

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Aswath Vs ,  Sundarrajan Rangachari ,  Sarma Sundareswara Gunturi ,  Sanjay Pennam

IPC: H03L7/10 ,  H03L7/099 ,  H03L7/089 ,  H03L7/197 ,  G06F7/58

Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseuodo-random pattern generator which provides the pseudo-random pattern.

公开(公告)号：US11469784B2

公开(公告)日：2022-10-11

申请号：US17001157

申请日：2020-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aswath Vs ,  Sthanunathan Ramakrishnan ,  Sriram Murali ,  Sarma Sundareswara Gunturi ,  Jaiganesh Balakrishnan ,  Sashidharan Venkatraman

IPC: H04B1/10 ,  H04B1/16

Abstract: One example includes a receiver system. The receiver system includes an analog-to-digital converter (ADC) configured to convert an analog input signal into a digital output signal at a sampling frequency. The receiver system also includes a spur correction system configured to receive the digital output signal and to estimate spurs associated with the digital output signal and to selectively correct a subset of the spurs associated with a set of frequencies that are based on the sampling frequency.

公开(公告)号：US11422586B1

公开(公告)日：2022-08-23

申请号：US17488559

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Aswath Vs ,  Sundarrajan Rangachari ,  Sarma Sundareswara Gunturi ,  Sanjay Pennam

IPC: G06F1/08 ,  G06F1/10

Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.

公开(公告)号：US11695602B2

公开(公告)日：2023-07-04

申请号：US17538460

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Nagalinga Swamy Basayya Aremallapur ,  Aswath Vs

IPC: H04L27/14

CPC classification number: H04L27/14

Abstract: A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.

公开(公告)号：US11476857B2

公开(公告)日：2022-10-18

申请号：US17072225

申请日：2020-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahul Sharma ,  Aswath Vs ,  Sriram Murali ,  Prasad Gandewar ,  Sandeep Kesrimal Oswal

IPC: H03M1/06 ,  H04L1/00 ,  H04W88/08

Abstract: Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to “pre-cancel” an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.