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公开(公告)号：US10163972B2
公开(公告)日：2018-12-25
申请号：US15092317
申请日：2016-04-06
Inventor： Hung-Wen Hsu , Jung-I Lin , Ching-Chung Su , Jiech-Fun Lu , Yeur-Luen Tu , Chia-Shiung Tsai
IPC: H01L27/146
Abstract: A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.
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公开(公告)号：US09337225B2
公开(公告)日：2016-05-10
申请号：US14026141
申请日：2013-09-13
Inventor： Hung-Wen Hsu , Jung-I Lin , Ching-Chung Su , Jiech-Fun Lu , Yeur-Luen Tu , Chia-Shiung Tsai
IPC: H01L27/146
CPC classification number: H01L27/14685 , H01L27/14623 , H01L27/1464 , H01L27/14643 , H01L27/14689
Abstract: A backside illumination semiconductor image sensing device includes a semiconductor substrate. The semiconductor substrate includes a radiation sensitive diode and a peripheral region. The peripheral region is proximal to a sidewall of the backside illumination semiconductor image sensing device. The backside illumination semiconductor image sensing device further includes a first anti reflective coating (ARC) on a backside of the semiconductor substrate and a dielectric layer on the first anti reflective coating. Additionally, a radiation shielding layer is disposed on the dielectric layer. Moreover, the backside illumination semiconductor image sensing device has a photon blocking layer on the sidewall of the backside illumination semiconductor image sensing device. The at least a portion of a sidewall of the radiation shielding layer is not covered by the photon blocking layer and the photon blocking layer is configured to block photons penetrating into the semiconductor substrate.
Abstract translation: 背面照明半导体图像感测装置包括半导体衬底。 半导体衬底包括辐射敏感二极管和外围区域。 外围区域靠近背侧照明半导体图像感测装置的侧壁。 背面照明半导体图像感测装置还包括在半导体衬底的背面上的第一抗反射涂层（ARC）和第一抗反射涂层上的介电层。 另外，辐射屏蔽层设置在电介质层上。 此外，背面照明半导体图像感测装置在背面照明半导体图像感测装置的侧壁上具有光子阻挡层。 辐射屏蔽层的侧壁的至少一部分未被光子阻挡层覆盖，并且光子阻挡层被配置为阻挡穿透到半导体衬底中的光子。
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公开(公告)号：US09293392B2
公开(公告)日：2016-03-22
申请号：US14020370
申请日：2013-09-06
Inventor： Shih Pei Chou , Hung-Wen Hsu , Ching-Chung Su , Chun-Han Tsao , Lin Chia-Chieh , Shu-Ting Tsai , Jiech-Fun Lu , Shih-Chang Liu , Yeur-Luen Tu , Chia-Shiung Tsai
IPC: H01L23/48 , H01L25/065 , H01L25/00 , H01L21/683 , H01L25/16
CPC classification number: H01L27/14634 , H01L21/6835 , H01L21/6836 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L27/14636 , H01L27/1464 , H01L2225/06544 , H01L2924/0002 , H01L2924/10253 , H01L2924/00
Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
Abstract translation: 提供了互连装置和形成互连装置的方法。 诸如晶片，管芯或晶片和管芯之类的两个基片结合在一起。 第一掩模用于形成部分地延伸到在第一晶片上形成的互连的第一开口。 形成电介质衬垫，然后使用相同的掩模进行另一蚀刻工艺。 蚀刻工艺继续暴露形成在第一衬底和第二衬底上的互连。 开口填充有导电材料以形成导电塞。
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公开(公告)号：US12218160B2
公开(公告)日：2025-02-04
申请号：US17249788
申请日：2021-03-12
Inventor： Wei-Lin Chen , Ching-Chung Su , Chun-Hao Chou , Kuo-Cheng Lee
IPC: H01L27/146
Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.
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公开(公告)号：US12154939B2
公开(公告)日：2024-11-26
申请号：US18360941
申请日：2023-07-28
Inventor： Ching-Sheng Chu , Dun-Nian Yaung , Yu-Cheng Tsai , Meng-Hsien Lin , Ching-Chung Su , Jen-Cheng Liu , Wen-De Wang , Guan-Hua Chen
Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
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Patent Agency Ranking
公开(公告)号：US20210036179A1
公开(公告)日：2021-02-04
申请号：US16865819
申请日：2020-05-04
Inventor： Chih Wei Sung , Chung-Bin Tseng , Keng-Ying Liao , Yen-Jou Wu , Po-Zen Chen , Su-Yu Yeh , Ching-Chung Su
IPC: H01L31/18
Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
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公开(公告)号：US10361234B2
公开(公告)日：2019-07-23
申请号：US15944069
申请日：2018-04-03
Inventor： Shih Pei Chou , Hung-Wen Hsu , Ching-Chung Su , Chun-Han Tsao , Chia-Chieh Lin , Shu-Ting Tsai , Jiech-Fun Lu , Shih-Chang Liu , Yeur-Luen Tu , Chia-Shiung Tsai
IPC: H01L27/146 , H01L23/48 , H01L25/065 , H01L21/768 , H01L25/00 , H01L21/683 , H01L25/16
Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
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公开(公告)号：US09984918B2
公开(公告)日：2018-05-29
申请号：US15088126
申请日：2016-04-01
Inventor： Ching-Chung Su , Jiech-Fun Lu , Jian Wu , Che-Hsiang Hsueh , Ming-Chi Wu , Chi-Yuan Wen , Chun-Chieh Fang , Yu-Lung Yeh
IPC: H01L21/764 , H01L21/762
CPC classification number: H01L21/764 , H01L21/3083 , H01L21/76232
Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
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公开(公告)号：US12183753B2
公开(公告)日：2024-12-31
申请号：US17483962
申请日：2021-09-24
Inventor： Wei-Lin Chen , Ching-Chung Su , Chun-Hao Chou , Kuo-Cheng Lee
IPC: H01L27/146 , G02F1/19
Abstract: An image sensor includes a first photodiode and a second photodiode. The image sensor further includes a first color filter over the first photodiode; and a second color filter over the second photodiode. The image sensor further includes a first microlens over the first color filter and a second microlens over the second color filter. The image sensor further includes a first electro-optical (EO) film between the first color filter and the first microlens, wherein a material of the first EO film is configured to change refractive index in response to application of an electrical field. The image sensor further includes a second EO film between the second color filter and the second microlens, wherein a material of the second EO film is configured to change refractive index in response to application of an electrical field.
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公开(公告)号：US20180226449A1
公开(公告)日：2018-08-09
申请号：US15944069
申请日：2018-04-03
Inventor： Shih Pei Chou , Hung-Wen Hsu , Ching-Chung Su , Chun-Han Tsao , Chia-Chieh Lin , Shu-Ting Tsai , Jiech-Fun Lu , Shih-Chang Liu , Yeur-Luen Tu , Chia-Shiung Tsai
IPC: H01L27/146 , H01L21/768 , H01L23/48 , H01L25/065 , H01L21/683 , H01L25/00 , H01L25/16
CPC classification number: H01L27/14634 , H01L21/6835 , H01L21/6836 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L27/14636 , H01L27/1464 , H01L2225/06544 , H01L2924/0002 , H01L2924/10253 , H01L2924/00
Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
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