公开(公告)号：US20230369389A1

公开(公告)日：2023-11-16

申请号：US18360941

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L21/20 ,  H01L29/94 ,  H01L29/66

CPC classification number: H01L28/75 ,  H01L28/87 ,  H01L28/88 ,  H01L28/92 ,  H01L29/945 ,  H01L29/66181 ,  H01L28/40

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

公开(公告)号：US20220181312A1

公开(公告)日：2022-06-09

申请号：US17680220

申请日：2022-02-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L25/16 ,  H01L33/00 ,  H01L33/62

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

公开(公告)号：US10790362B2

公开(公告)日：2020-09-29

申请号：US15962454

申请日：2018-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yao-Wen Chang ,  Gung-Pei Chang ,  Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.

公开(公告)号：US20230335543A1

公开(公告)日：2023-10-19

申请号：US18332069

申请日：2023-06-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L25/16 ,  H01L33/00 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L33/0093 ,  H01L33/0095 ,  H01L33/62 ,  H01L2933/0066

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

公开(公告)号：US11721683B2

公开(公告)日：2023-08-08

申请号：US17680220

申请日：2022-02-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L25/16 ,  H01L33/00 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L33/0093 ,  H01L33/0095 ,  H01L33/62 ,  H01L2933/0066

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

公开(公告)号：US20220115349A1

公开(公告)日：2022-04-14

申请号：US17555854

申请日：2021-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.

公开(公告)号：US12154939B2

公开(公告)日：2024-11-26

申请号：US18360941

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L29/66 ,  H01L29/94 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

公开(公告)号：US12087826B2

公开(公告)日：2024-09-10

申请号：US17816308

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yao-Wen Chang ,  Gung-Pei Chang ,  Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L29/26 ,  H01L21/02172 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76889

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A sacrificial layer is formed conforming to the high-k dielectric layer.

公开(公告)号：US11735550B2

公开(公告)日：2023-08-22

申请号：US17555854

申请日：2021-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L24/16 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/11 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/37001

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.

公开(公告)号：US20240387613A1

公开(公告)日：2024-11-21

申请号：US18783569

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01G4/30 ,  H01L29/66 ,  H01L29/94

Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.