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公开(公告)号:US10283599B2
公开(公告)日:2019-05-07
申请号:US15670135
申请日:2017-08-07
发明人: Fu-Wei Yao , Chun-Wei Hsu , Chen-Ju Yu , Jiun-Lei Jerry Yu , Fu-Chih Yang , Chih-Wen Hsiung , King-Yuen Wong
IPC分类号: H01L29/20 , H01L29/40 , H01L29/66 , H01L29/778
摘要: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
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公开(公告)号:US10164047B2
公开(公告)日:2018-12-25
申请号:US15443861
申请日:2017-02-27
发明人: Chen-Ju Yu , Chih-Wen Hsiung , Fu-Wei Yao , Chun-Wei Hsu , King-Yuen Wong , Jiun-Lei Jerry Yu , Fu-Chih Yang
IPC分类号: H01L29/20 , H01L29/778 , H01L29/66 , H01L21/02 , H01L29/423 , H01L29/10 , H01L21/225 , H01L21/3065 , H01L21/3205 , H01L21/321 , H01L21/3213 , H01L21/324 , H01L29/201 , H01L29/205 , H01L29/06 , H01L29/08
摘要: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
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公开(公告)号:US09748372B2
公开(公告)日:2017-08-29
申请号:US14926783
申请日:2015-10-29
发明人: King-Yuen Wong , Chen-Ju Yu , Fu-Wei Yao , Chun-Wei Hsu , Jiun-Lei Jerry Yu , Chih-Wen Hsiung , Fu-Chih Yang
IPC分类号: H01L29/778 , H01L29/51 , H01L29/66 , H01L21/28 , H01L29/20 , H01L29/207
CPC分类号: H01L29/7786 , H01L21/28264 , H01L29/2003 , H01L29/207 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7787
摘要: A method of forming a semiconductor structure includes growing a second III-V compound layer over a first III-V compound layer, wherein the second III-V compound layer has a different band gap from the first III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, the source feature and the drain feature. The method further includes implanting at least one fluorine-containing compound into a portion of the gate dielectric layer. The method further includes forming a gate electrode over the portion of the gate dielectric layer.
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公开(公告)号:US09728613B2
公开(公告)日:2017-08-08
申请号:US14855460
申请日:2015-09-16
发明人: Fu-Wei Yao , Chun-Wei Hsu , Chen-Ju Yu , Jiun-Lei Jerry Yu , Fu-Chih Yang , Chih-Wen Hsiung , King-Yuen Wong
IPC分类号: H01L29/66 , H01L29/40 , H01L29/778 , H01L29/20
CPC分类号: H01L29/402 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
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公开(公告)号:US09583588B2
公开(公告)日:2017-02-28
申请号:US14533864
申请日:2014-11-05
发明人: Chen-Ju Yu , Chih-Wen Hsiung , Fu-Wei Yao , Chun-Wei Hsu , King-Yuen Wong , Jiun-Lei Jerry Yu , Fu-Chih Yang
IPC分类号: H01L29/778 , H01L29/06 , H01L21/335 , H01L21/336 , H01L29/66 , H01L29/423 , H01L29/10 , H01L29/20 , H01L21/02 , H01L21/225 , H01L21/3065 , H01L21/3205 , H01L21/321 , H01L21/3213 , H01L21/324 , H01L29/201 , H01L29/205
CPC分类号: H01L29/66462 , H01L21/0254 , H01L21/2258 , H01L21/3065 , H01L21/32051 , H01L21/321 , H01L21/32133 , H01L21/324 , H01L29/0653 , H01L29/0843 , H01L29/1029 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/66431 , H01L29/7787
摘要: A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.
摘要翻译: 一种方法包括在硅衬底上外延生长氮化镓(GaN)层。 该方法还包括在GaN层上外延生长施主供体层。 该方法还包括在供体层上形成源极和漏极。 该方法还包括在供体层上的源极和漏极之间形成栅极结构。 该方法还包括将供体供体层的漂移区域的一部分等离子体蚀刻到小于施主供体层厚度的60%的深度。 该方法还包括在供体供体层上沉积介电层。
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公开(公告)号:US09455341B2
公开(公告)日:2016-09-27
申请号:US13944672
申请日:2013-07-17
发明人: Chi-Ming Chen , Chih-Wen Hsiung , Po-Chun Liu , Ming-Chang Ching , Chung-Yi Yu , Xiaomeng Chen
IPC分类号: H01L29/778 , H01L29/66 , H01L29/20
CPC分类号: H01L29/7783 , H01L29/2003 , H01L29/66462
摘要: A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.
摘要翻译: 晶体管包括衬底和衬底上的缓冲层,其中缓冲层包括p型掺杂剂。 晶体管还包括缓冲层上的沟道层和沟道层的第一部分和沟道层的第二部分之间的背面阻挡层。 后阻挡层与沟道层具有带隙不连续性。 晶体管还包括在沟道层的第二部分上的有源层,其中有源层与沟道层的第二部分具有带隙不连续性。 晶体管还包括在沟道层中与沟道层和有源层之间的界面相邻的二维电子气(2-DEG)。
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公开(公告)号:US10811261B2
公开(公告)日:2020-10-20
申请号:US16003110
申请日:2018-06-08
发明人: Ming-Wei Tsai , King-Yuen Wong , Chih-Wen Hsiung , Ming-Cheng Lin
IPC分类号: H01L21/22 , H01L21/283 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/778 , H01L21/28 , H01L21/765 , H01L21/768 , H01L21/02 , H01L21/285 , H01L21/8234 , H01L29/20
摘要: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
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公开(公告)号:US10056478B2
公开(公告)日:2018-08-21
申请号:US14935342
申请日:2015-11-06
发明人: Ming-Wei Tsai , King-Yuen Wong , Chih-Wen Hsiung , Ming-Cheng Lin
IPC分类号: H01L29/778 , H01L29/40 , H01L29/66 , H01L29/423 , H01L29/20
CPC分类号: H01L29/778 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/404 , H01L29/42316 , H01L29/66409 , H01L29/66431 , H01L29/66462 , H01L29/7786 , H01L2229/00
摘要: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
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公开(公告)号:US10002955B2
公开(公告)日:2018-06-19
申请号:US15481008
申请日:2017-04-06
发明人: Ming-Wei Tsai , King-Yuen Wong , Chih-Wen Hsiung , Ming-Cheng Lin
IPC分类号: H01L29/778 , H01L29/66
CPC分类号: H01L29/778 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/404 , H01L29/42316 , H01L29/66409 , H01L29/66431 , H01L29/66462 , H01L29/7786 , H01L2229/00
摘要: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
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公开(公告)号:US09343542B2
公开(公告)日:2016-05-17
申请号:US14550521
申请日:2014-11-21
IPC分类号: H01L21/338 , H01L21/322 , H01L29/66 , H01L29/205 , H01L29/207 , H01L21/02 , H01L29/10 , H01L29/20 , H01L29/423 , H01L29/778
CPC分类号: H01L29/66462 , H01L21/0254 , H01L21/0262 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/42316 , H01L29/66143 , H01L29/7787
摘要: A method for making an enhancement-mode transistor is described. The method includes forming a first III-V compound layer on a substrate and forming a second III-V compound layer on the first III-V compound layer. The second III-V compound layer is different from the first III-V compound layer. A gate stack is formed thereon. The forming of the gate stack further includes forming a diode having a pair of a n-type doped III-V compound layer and a p-type doped III-V compound layer. Source and drain features are formed on the second III-V compound layer and interposed by the gate stack.
摘要翻译: 描述制造增强型晶体管的方法。 该方法包括在衬底上形成第一III-V化合物层,并在第一III-V化合物层上形成第二III-V化合物层。 第二III-V化合物层与第一III-V族化合物层不同。 在其上形成栅极堆叠。 栅堆叠的形成还包括形成具有一对n型掺杂III-V化合物层和p型掺杂III-V化合物层的二极管。 源极和漏极特征形成在第二III-V复合层上并由栅极叠层插入。
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