公开(公告)号：US5511173A

公开(公告)日：1996-04-23

申请号：US177794

申请日：1994-01-05

Applicant: Shinichi Yamaura ,  Takashi Yasui ,  Keiichi Yoshioka

Inventor： Shinichi Yamaura ,  Takashi Yasui ,  Keiichi Yoshioka

IPC: G06F9/32 ,  G06F9/22 ,  H03K19/177 ,  G06F9/30

CPC classification number: H03K19/1772 ,  G06F9/223

Abstract: A programmable logic array includes a plurality of AND planes. Each AND plane executes an AND logic operation and has input terminals and output terminals. The programmable logic array also includes a single OR plane provided in common for the plurality of AND planes. The single OR plane executes an OR logic operation and has input terminals coupled to the output terminals of the plurality of AND planes and output terminals. A data processing unit using the above programmable logic array is also provided.

Abstract translation: 可编程逻辑阵列包括多个AND平面。 每个AND平面执行AND逻辑运算，并具有输入端和输出端。 可编程逻辑阵列还包括为多个AND平面共同提供的单个OR平面。 单OR平面执行或逻辑运算，并且具有耦合到多个AND平面和输出端的输出端的输入端。 还提供了使用上述可编程逻辑阵列的数据处理单元。

公开(公告)号：US5301338A

公开(公告)日：1994-04-05

申请号：US568827

申请日：1990-08-17

Applicant: Shinichi Yamaura ,  Takashi Yasui ,  Keiichi Yoshioka

Inventor： Shinichi Yamaura ,  Takashi Yasui ,  Keiichi Yoshioka

IPC: G06F7/50 ,  G06F7/00 ,  G06F7/507 ,  G06F9/302 ,  G06F9/305 ,  G06F9/308 ,  G06F12/00 ,  G06F12/04

CPC classification number: G06F9/30014 ,  G06F9/30018

Abstract: A central processing unit includes a programmable logic array, a timing control unit, a predecoder, a data input/output part, and a processing part. The processing part carries out a predetermined operation on m-bit low-order data from among data which is composed of n bits and which is read out from a memory and m-bit high-order data from among the data composed of n bits, and outputs a carry signal when the predetermined operation on the m-bit low-order data results in a carry. When the operation code is a read modify write instruction and when the processing part outputs the carry signal, the programmable logic array controls the input/output part so that only the result of the predetermined operation on the m-bit low-order data is written into the memory.

Abstract translation: 中央处理单元包括可编程逻辑阵列，定时控制单元，预解码器，数据输入/输出部分和处理部分。 处理部分从由n位组成的数据和从n位组成的数据中从存储器读出的m位低位数据中的m位低位数据执行预定的操作， 并且当对m位低位数据的预定操作导致进位时，输出进位信号。 当操作代码是读修改写指令时，当处理部分输出进位信号时，可编程逻辑阵列控制输入/输出部分，使得仅对m位低位数据进行预定操作的结果被写入 进入记忆。

公开(公告)号：US5596761A

公开(公告)日：1997-01-21

申请号：US101399

申请日：1993-08-02

Applicant: Keiichi Yoshioka ,  Takashi Yasui ,  Shinichi Yamaura

Inventor： Keiichi Yoshioka ,  Takashi Yasui ,  Shinichi Yamaura

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC classification number: G06F9/3861 ,  G06F9/32

Abstract: A central processing unit (CPU) carries out selected reset interruption processing by using a vector address preset in accordance with an interruption source to generate an address to a data table whose contents are used to initialize selected registers. In this manner, the CPU can be reset without having first stored the processing state of the CPU in response to a reset interrupt request, without the need for extensive dedicated reset hardware, and with the ability to select desired reset values that can differ as between different interrupts and can be changed from time to time.

Abstract translation: 中央处理单元（CPU）通过使用根据中断源预设的向量地址来执行所选择的复位中断处理，以将内容生成到其内容用于初始化所选择的寄存器的数据表。 以这种方式，CPU可以被复位而不需要首先存储CPU的处理状态，而不需要广泛的专用复位硬件，并且具有选择期望的复位值的能力，所述复位值可以不同 不同的中断，可以不时更改。

公开(公告)号：US5161229A

公开(公告)日：1992-11-03

申请号：US533383

申请日：1990-06-05

Applicant: Takashi Yasui ,  Keiichi Yoshioka ,  Shinichi Yamaura

Inventor： Takashi Yasui ,  Keiichi Yoshioka ,  Shinichi Yamaura

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/3861

Abstract: A central processing unit has a plurality of control sections; a device for selectively operating and unoperating the control sections by an external interrruption signal; and a device for processing an interruption sequence with respect to the interruption signal by the operations of the control sections in a state in which the control sections are operated. The control processing unit may be constructed such that the control sections are composed of two control sections and one of the two control sections processes a normal instruction sequence and is unoperated by the interruption signal, and the other of the two control sections is operated at the times of the normal instruction and interruption and processes the interruption sequence in addition to the normal instruction.

Abstract translation: 中央处理单元具有多个控制部分; 用于通过外部中断信号选择性地操作和不操作所述控制部分的装置; 以及用于在控制部分被操作的状态下通过控制部分的操作来处理关于中断信号的中断序列的装置。 控制处理单元可以被构造成使得控制部分由两个控制部分组成，并且两个控制部分中的一个控制部分处理正常指令序列并且由中断信号进行未操作，并且两个控制部分中的另一个在 正常指令的次数和中断，并处理除了正常指令之外的中断序列。

公开(公告)号：US5696957A

公开(公告)日：1997-12-09

申请号：US593482

申请日：1996-01-29

Applicant: Shinichi Yamaura ,  Kazuhiko Hara ,  Keiichi Yoshioka ,  Takashi Yasui

Inventor： Shinichi Yamaura ,  Kazuhiko Hara ,  Keiichi Yoshioka ,  Takashi Yasui

IPC: G06F9/30 ,  G06F9/46

CPC classification number: G06F9/3012 ,  G06F9/462

Abstract: An integrated circuit has a central processing unit for executing programs. The integrated circuit includes a register set, provided in the central processing unit, for storing crate required for executing a program in the central processing unit; and a register-file RAM, coupled to the central processing unit, for storing at least the same data as that stored in the register set in the central processing unit, wherein data stored in the register-file RAM can be supplied to the register set in the central processing unit.

Abstract translation: 集成电路具有用于执行程序的中央处理单元。 集成电路包括设置在中央处理单元中的寄存器组，用于存储在中央处理单元中执行程序所需的箱; 以及耦合到中央处理单元的寄存器文件RAM，用于存储至少与存储在中央处理单元中的寄存器中的数据相同的数据，其中存储在寄存器文件RAM中的数据可以被提供给寄存器组 在中央处理单位。

公开(公告)号：US4922441A

公开(公告)日：1990-05-01

申请号：US143715

申请日：1988-01-14

Applicant: Toshihiro Tsukagoshi ,  Masanobu Fukushima ,  Keiichi Yoshioka ,  Takashi Yasui

Inventor： Toshihiro Tsukagoshi ,  Masanobu Fukushima ,  Keiichi Yoshioka ,  Takashi Yasui

IPC: G11C11/412 ,  G11C17/12 ,  H01L27/11 ,  H01L27/118 ,  H03K19/173 ,  G06F15/60

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C17/12 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/118 ,  H03K19/1735

Abstract: A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.

Abstract translation: 门阵列器件包括彼此间隔开的多个基本单元区域，从而在其间限定多个中间区域。 每个中间区域可以至少部分地用作存储器或功能单元区域或者作为互连区域。 可以通过金属化将存储单元区域选择性地定义为ROM或RAM。 可以根据控制信号选择性地设置测试模式或正常操作模式。 当正常操作模式被设置时，输入端通过逻辑电路可操作地连接到存储器电路; 而当设置测试模式时，输入端直接连接到存储器电路，同时旁路逻辑电路。 还提供了一种存储单元结构，其可以被定义为RAM存储器单元或者通过金属化存储选择的二进制数据的ROM存储单元。

公开(公告)号：US08442939B2

公开(公告)日：2013-05-14

申请号：US12388174

申请日：2009-02-18

Applicant: Takashi Yasui ,  Masaaki Shimizu

Inventor： Takashi Yasui ,  Masaaki Shimizu

IPC: G06F7/00 ,  G06F17/00

CPC classification number: G06F17/30168 ,  G06F2221/2147

Abstract: Provided is a computer system including a plurality of computing hosts, which constructs a shared file system dynamically so that job execution efficiency is improved. In the computer system which includes the plurality of computing hosts and executes a job requested, in a case where the job is executed by the plurality of computing hosts, each computing host which executes the job is configured to: share a file necessary for executing the job; access the shared file to execute the requested job; and cancel the sharing of the file after execution of the requested job is completed.

Abstract translation: 提供了一种包括多个计算主机的计算机系统，其动态地构建共享文件系统，从而提高作业执行效率。 在包括多个计算主机并执行所请求的作业的计算机系统中，在由多个计算主机执行作业的情况下，执行该作业的每个计算主机被配置为：共享执行所需的文件 工作; 访问共享文件以执行请求的作业; 并在完成所请求的作业的执行后取消共享文件。

公开(公告)号：US20070287077A1

公开(公告)日：2007-12-13

申请号：US11802005

申请日：2007-05-18

Applicant: Katsuhiro Takushima ,  Takashi Yasui

Inventor： Katsuhiro Takushima ,  Takashi Yasui

IPC: A47G1/12 ,  G03F1/14 ,  G03F1/00

CPC classification number: G03F1/64 ,  G03F1/62

Abstract: To provide a photomask capable of preventing a foreign matter generation in using the photomask, and an exposure method using this photomask. The photomask includes a transparent substrate 2; a transfer pattern 4 formed in a main region 3 of a center portion of the transparent substrate 2; a light-shading band region 5 provided adjacent to the main region 3 in the outer peripheral region of the main region 3; and a pellicle 6 formed by adhering a pellicle film 6a to a pellicle frame 6b by an adhesive 8a, wherein this pellicle 6 is adhered onto a light-shading region 7 consisting of a light-shading film formed in the outer peripheral region of the main region 3, through an adhesive 8b.

Abstract translation: 提供能够防止在使用光掩模中产生异物的光掩模和使用该光掩模的曝光方法。 光掩模包括透明基板2; 形成在透明基板2的中心部分的主区域3中的转印图案4; 在主区域3的外周区域中与主区域3相邻设置的遮光带区域5; 以及通过粘合剂8a将防护薄膜6a粘附在防护薄膜组件6b上形成的防护薄膜组件6，其中该防护薄膜组件6粘附在由形成在外围区域中的遮光膜构成的遮光区域7上 的主区域3，通过粘合剂8b。

公开(公告)号：US4043801A

公开(公告)日：1977-08-23

申请号：US598756

申请日：1975-07-25

Applicant: Eiichi Sakamoto ,  Masanobu Kubo ,  Takashi Yasui ,  Katsuya Suzuki ,  Katsuhiko Tachibana

Inventor： Eiichi Sakamoto ,  Masanobu Kubo ,  Takashi Yasui ,  Katsuya Suzuki ,  Katsuhiko Tachibana

IPC: C21C5/30

CPC classification number: C21C5/30

Abstract: In the refining of steel by an oxygen topblown converter, the temperature and carbon content of molten steel are simultaneously measured by a sensor at a predetermined time before the end point, whereby in accordance with the difference between a calculated carbon content at the endpoint obtained by processing the measured values and a target carbon content at the end-point, the oxygen quantity to be blown in at the end-point and the coolant requirement or the pattern of soft-blow are computed to simultaneously control the temperature and carbon content of the molten steel at the end-point.

Abstract translation: 在通过氧气顶吹转化器精炼钢中，在端点之前的预定时间，通过传感器同时测量钢水的温度和碳含量，由此根据由终点获得的计算得到的碳含量之差 在终点处理测量值和目标碳含量，计算在终点吹入的氧气量和冷却液要求或软吹模式，以同时控制温度和碳含量 钢水终点。

公开(公告)号：US12066508B2

公开(公告)日：2024-08-20

申请号：US17429479

申请日：2020-03-16

Applicant: Takashi Yasui

Inventor： Takashi Yasui

IPC: G01R33/035 ,  A61B5/243 ,  A61B5/245 ,  A61B5/248 ,  H03H17/02

CPC classification number: G01R33/0356 ,  A61B5/243 ,  A61B5/245 ,  A61B5/248 ,  H03H17/02 ,  A61B2562/0223

Abstract: A magnetic field measuring apparatus includes an A/D conversion unit, an integration unit, and a post-processing unit. The A/D conversion unit is configured to sample a signal at a predetermined sampling frequency and perform conversion into digital data, the signal being based on an output voltage from a superconducting quantum interference device configure to detect a magnetic field emanating from a living organism. The integration unit is configured to obtain a biological magnetic field signal based on a value obtained by integrating the digital data, the biological magnetic field signal indicating a magnetic field emanating from the living organism. The post-processing unit is configured to perform decimation processing on the biological magnetic field signal output from the integration unit.