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    Fault-tolerant unit and method for through-silicon via
    1.
    发明授权
    Fault-tolerant unit and method for through-silicon via 有权
    容错单元和穿硅通孔的方法

    公开(公告)号：US09177940B2

    公开(公告)日：2015-11-03

    申请号：US13236661

    申请日：2011-09-20

    申请人： Chiao-Ling Lung ,  Yu-Shih Su ,  Shih-Chieh Chang ,  Yiyu Shi

    发明人： Chiao-Ling Lung ,  Yu-Shih Su ,  Shih-Chieh Chang ,  Yiyu Shi

    IPC分类号： H03K19/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

    CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2225/06544

    摘要： A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a switching module. The TSV structure TSVi is connected between the node N1i of the first chip and the node N2i of the second chip, wherein 1≦i≦n. The switching module is connected between the nodes N21˜N2n of the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N21˜N2n when the TSV structures TSV1˜TSVn are valid. The switching module connects the node N2i to at least another one of the nodes N21˜N2n when the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N21˜N2n.

    摘要翻译： 提供了一种容错单元和通过硅通孔（TSV）的容错方法。 容错单元包括TSV结构TSV1〜TSVn，节点N11〜N1n，节点N21〜Nn以及交换模块。 TSV结构TSVi连接在第一芯片的节点N1i和第二芯片的节点N2i之间，其中1＆nlE; i＆nlE; n。 切换模块连接在第二芯片的节点N21〜Nn2和第二芯片的测试路径之间。 在正常工作状态下，当TSV结构TSV1〜TSVn有效时，切换模块断开测试路径和节点N21〜N2。 当TSV结构TSVi在正常操作状态下故障时，切换模块将节点N2i连接到节点N21〜Nnn中的至少另一个。 在测试状态下，交换模块将测试路径连接到节点N21〜N2n。

    Semiconductor package structure
    3.
    发明授权
    Semiconductor package structure 有权
    半导体封装结构

    公开(公告)号：US08581384B2

    公开(公告)日：2013-11-12

    申请号：US13426804

    申请日：2012-03-22

    申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

    发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/16245

    摘要： A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

    摘要翻译： 半导体封装结构包括引线框架，至少一个芯片，模塑料和抗导电膜。 引线框架包括多个引线，每个引线包括第一端部和第二端部，其中第一端部包括第一上表面和第一下表面，并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。

    POWER-MODE-AWARE CLOCK TREE AND SYNTHESIS METHOD THEREOF
    7.
    发明申请
    POWER-MODE-AWARE CLOCK TREE AND SYNTHESIS METHOD THEREOF 有权
    功率模式时钟树及其合成方法

    公开(公告)号：US20110121875A1

    公开(公告)日：2011-05-26

    申请号：US12750721

    申请日：2010-03-31

    申请人： Chiao-Ling Lung ,  Shih-Chieh Chang

    发明人： Chiao-Ling Lung ,  Shih-Chieh Chang

    IPC分类号： H03L7/00 ,  G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/62

    摘要： A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.

    摘要翻译： 提供了功率模式感知（PMA）时钟树及其合成方法。 时钟树包括子时钟树和PMA缓冲区。 子时钟树将延迟的时钟信号发送到功能模块，其中根据功率信息确定功能模块的功率模式。 PMA缓冲器耦合到子时钟树。 PMA缓冲器根据功率信息确定系统时钟信号的延迟时间延迟系统时钟信号，并将延迟的系统时钟信号作为延迟的时钟信号输出到子时钟树。

    Semiconductor memory device and power control method thereof
    8.
    发明申请
    Semiconductor memory device and power control method thereof 审中-公开
    半导体存储器件及其功率控制方法

    公开(公告)号：US20080219083A1

    公开(公告)日：2008-09-11

    申请号：US12073507

    申请日：2008-03-06

    申请人： Shih-Chieh Chang

    发明人： Shih-Chieh Chang

    IPC分类号： G11C8/18

    CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G06F5/12 ,  Y02D10/13 ,  Y02D10/14

    摘要： A semiconductor memory device for saving power consumption and control method thereof are disclosed. The clock frequency on memory chips is dynamically adjusted to match the data transferring rate between the other units in computer system and the memory chips. A fill state of buffer and transferring rate on an input/output interface are detected by a monitor. A frequency adjuster increases or decrease the clock frequency on memory chips for keeping a good transferring rate and saving unnecessary power according to the monitor's detection.

    摘要翻译： 公开了一种用于节省功耗的半导体存储器件及其控制方法。 动态地调整存储器芯片上的时钟频率以匹配计算机系统中的其他单元和存储器芯片之间的数据传输速率。 监视器检测输入/输出接口上的缓冲区和传输速率的填充状态。 频率调节器增加或减少存储芯片上的时钟频率，以保持良好的传输速率，并根据显示器的检测节省不必要的电力。

    VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF
    9.
    发明申请
    VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF 有权
    威盛/联系人和丹麦结构及其制造方法

    公开(公告)号：US20080211106A1

    公开(公告)日：2008-09-04

    申请号：US11680981

    申请日：2007-03-01

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/7684

    摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

    摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。