公开(公告)号：US07447079B2

公开(公告)日：2008-11-04

申请号：US11771982

申请日：2007-06-29

Applicant: Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu ,  Nima Mokhlesi ,  Deepak Chandra Sekar

Inventor： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu ,  Nima Mokhlesi ,  Deepak Chandra Sekar

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5634 ,  G11C2211/565

Abstract: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract translation: 在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。 控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。 源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。 即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。 通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

公开(公告)号：US20070297234A1

公开(公告)日：2007-12-27

申请号：US11848385

申请日：2007-08-31

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract translation: 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US20060140007A1

公开(公告)日：2006-06-29

申请号：US11026536

申请日：2004-12-29

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Chan

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Chan

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Abstract translation: 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

公开(公告)号：US20050169051A1

公开(公告)日：2005-08-04

申请号：US11064529

申请日：2005-02-22

Applicant: Shahzad Khalid ,  Daniel Guterman ,  Geoffrey Gongwer ,  Richard Simko ,  Kevin Conley

Inventor： Shahzad Khalid ,  Daniel Guterman ,  Geoffrey Gongwer ,  Richard Simko ,  Kevin Conley

IPC: G11C7/06 ,  G11C7/14 ,  G11C11/34 ,  G11C11/56 ,  G11C27/00

CPC classification number: G11C7/14 ,  G11C7/06 ,  G11C11/5642 ,  G11C27/005 ,  G11C2211/5634

Abstract: The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.

Abstract translation: 本发明提出了使用可写跟踪单元的几种技术。 为存储器的每个写入块提供多个跟踪单元。 每当相关联的写入块的用户单元被优选地同时使用相同的固定的全局参考电平来写入时，这些单元被重新编程，以设置跟踪和用户单元编程的阈值。 每次读取用户单元时，读取跟踪单元的阈值电压，并且这些阈值用于确定用户单元的存储的逻辑电平。 在一组实施例中，一个或多个跟踪单元的群体与多状态存储器的不同逻辑电平相关联。 这些跟踪单元群可以仅提供逻辑电平的子集。 基于该子集，针对所有逻辑电平导出用于转换阈值电压的读取点。 在一个实施例中，由多个跟踪单元组成的两个群组与多位单元的两个逻辑电平相关联。 在模拟实现中，使用跟踪单元格群体的模拟阈值直接读取用户单元，而不首先将其转换为数字值。 一组替代实施例提供使用不同的电压和/或定时来跟踪单元的写入，以便在跟踪单元的最终写入阈值中提供较小的不确定性。

公开(公告)号：US06747892B2

公开(公告)日：2004-06-08

申请号：US09989996

申请日：2001-11-20

Applicant: Shahzad Khalid

Inventor： Shahzad Khalid

IPC: G11C1604

CPC classification number: G11C11/5642 ,  G11C7/06 ,  G11C7/062 ,  G11C7/12

Abstract: A sense amplifier (100) useable with memories having multi-level memory cells (105) includes a cascode device (135) coupled to the cell (105) to increase sense amplifier resolution. In a pre-charge mode, the sense amplifier (100) is configured to pre-charge a bit-line (140) of the cell (105) to reduce time required to read the cell. The pre-charge mode may include a unity gain buffer (175) to which a reference voltage is applied, and a switch (165, 170). The switch (165, 170) couples the buffer to the cascode device (135) to pre-charge the bit-line (140), and decouples the buffer from the device to enable the amplifier (100) to develop a voltage signal representing data stored in the cell. The sense amplifier (100) can be re-configured in a regeneration mode to amplify the voltage signal, to conserve chip space, and reduce cost and errors in reads.

Abstract translation: 可用于具有多级存储器单元（105）的存储器的读出放大器（100）包括耦合到单元（105）以增加读出放大器分辨率的共源共栅器件（135）。 在预充电模式中，读出放大器（100）被配置为对单元（105）的位线（140）进行预充电以减少读取单元所需的时间。 预充电模式可以包括施加参考电压的单位增益缓冲器（175）和开关（165,170）。 开关（165,170）将缓冲器耦合到共源共用器件（135）以对位线（140）预充电，并且将缓冲器与器件去耦，以使放大器（100）能够产生表示数据的电压信号 存储在单元格中。 读出放大器（100）可以在再生模式下重新配置以放大电压信号，以节省芯片空间，并且降低读取中的成本和错误。

公开(公告)号：US20110141816A1

公开(公告)日：2011-06-16

申请号：US13031041

申请日：2011-02-18

Applicant: Daniel C. Guterman ,  Stephen J. Gross ,  Shahzad Khalid ,  Geoffrey S. Gongwer

Inventor： Daniel C. Guterman ,  Stephen J. Gross ,  Shahzad Khalid ,  Geoffrey S. Gongwer

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C16/349

Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Read operations are performed on the tracking cells, where threshold voltages of physical states of the tracking cells are further apart than threshold voltages of physical states of non-tracking cells. Based on the read operations, an extent to which the tracking cells are errored is determined.

Abstract translation: 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 在跟踪单元上执行读操作，其中跟踪单元的物理状态的阈值电压比非跟踪单元的物理状态的阈值电压更远。 基于读取操作，确定跟踪单元被错误的程度。

公开(公告)号：US07681094B2

公开(公告)日：2010-03-16

申请号：US11752024

申请日：2007-05-22

Applicant: Daniel C. Guterman ,  Stephen J. Gross ,  Shahzad Khalid ,  Geoffrey S. Gongwer

Inventor： Daniel C. Guterman ,  Stephen J. Gross ,  Shahzad Khalid ,  Geoffrey S. Gongwer

IPC: G11C29/00 ,  G06F13/00

CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C16/349

Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

Abstract translation: 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

公开(公告)号：US07532514B2

公开(公告)日：2009-05-12

申请号：US11848385

申请日：2007-08-31

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract translation: 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US20060227614A1

公开(公告)日：2006-10-12

申请号：US11422034

申请日：2006-06-02

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract translation: 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US07002401B2

公开(公告)日：2006-02-21

申请号：US10356098

申请日：2003-01-30

Applicant: Shahzad Khalid

Inventor： Shahzad Khalid

IPC: G05F1/10

CPC classification number: G11C27/005 ,  G11C27/028 ,  H03F1/342 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/297 ,  H03F2200/366 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/5021 ,  H03F2203/5027

Abstract: A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level as the transistor in the feedback loop and provide an output voltage based on the reference input voltage. The output voltage is dependent upon the input voltage, but the load is removed from the feedback loop. By removing the load from the feedback loop, the loop is stabilized with only a very small or no compensating capacitor, allowing the quiescent current of the buffer to be reduced and the settling time to be improved. One preferred use of the present invention is to drive the data storage elements of a non-volatile memory.

Abstract translation: 用于电容负载的电压缓冲器将负载与反馈回路隔离。 使用从动装置的变型，引入反馈回路外部的第二晶体管。 通过第二晶体管提供到负载的电流，第二晶体管被连接以具有与反馈回路中的晶体管相同的控制栅极电平，并且基于参考输入电压提供输出电压。 输出电压取决于输入电压，但负载从反馈回路中移除。 通过从反馈回路中消除负载，仅通过非常小的补偿电容器或无补偿电容器使环路稳定，从而可以减小缓冲器的静态电流并提高稳定时间。 本发明的一个优选的用途是驱动非易失性存储器的数据存储元件。