公开(公告)号：US20060140007A1

公开(公告)日：2006-06-29

申请号：US11026536

申请日：2004-12-29

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Chan

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Chan

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Abstract translation: 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

公开(公告)号：US20070263450A1

公开(公告)日：2007-11-15

申请号：US11781917

申请日：2007-07-23

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Chan

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Chan

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Abstract translation: 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

公开(公告)号：US20090103369A1

公开(公告)日：2009-04-23

申请号：US12342679

申请日：2008-12-23

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

IPC: G11C16/06 ,  G11C11/10

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Abstract translation: 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

公开(公告)号：US07471575B2

公开(公告)日：2008-12-30

申请号：US11781917

申请日：2007-07-23

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

IPC: G11C7/10

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Abstract translation: 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

公开(公告)号：US06956770B2

公开(公告)日：2005-10-18

申请号：US10667223

申请日：2003-09-17

Applicant: Shahzad Khalid ,  Yan Li ,  Raul-Adrian Cernea ,  Mehrdad Mofidi

Inventor： Shahzad Khalid ,  Yan Li ,  Raul-Adrian Cernea ,  Mehrdad Mofidi

IPC: G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3468 ,  G11C16/0483

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

公开(公告)号：US20050057967A1

公开(公告)日：2005-03-17

申请号：US10667223

申请日：2003-09-17

Applicant: Shahzad Khalid ,  Yan Li ,  Raul-Adrian Cernea ,  Mehrdad Mofidi

Inventor： Shahzad Khalid ,  Yan Li ,  Raul-Adrian Cernea ,  Mehrdad Mofidi

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/34

CPC classification number: G11C16/3468 ,  G11C16/0483

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract translation: 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量作为电压偏移量加到编程中存储单元的位线。 电压偏移是否是其邻居中的一个或两个或两个都处于产生扰动的模式中的预定函数，例如在程序禁止模式中。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US20070297234A1

公开(公告)日：2007-12-27

申请号：US11848385

申请日：2007-08-31

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract translation: 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US07532514B2

公开(公告)日：2009-05-12

申请号：US11848385

申请日：2007-08-31

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract translation: 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US20060227614A1

公开(公告)日：2006-10-12

申请号：US11422034

申请日：2006-06-02

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Mehrdad Mofidi ,  Shahzad Khalid

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract translation: 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

公开(公告)号：US20110019485A1

公开(公告)日：2011-01-27

申请号：US12900443

申请日：2010-10-07

Applicant: Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

Inventor： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Abstract translation: 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。