Invention Grant
US07532514B2 Non-volatile memory and method with bit line to bit line coupled compensation
有权
非易失性存储器和方式与位线到位线耦合补偿
- Patent Title: Non-volatile memory and method with bit line to bit line coupled compensation
- Patent Title (中): 非易失性存储器和方式与位线到位线耦合补偿
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Application No.: US11848385Application Date: 2007-08-31
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Publication No.: US07532514B2Publication Date: 2009-05-12
- Inventor: Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
- Applicant: Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
- Applicant Address: US CA Milpitas
- Assignee: Sandisk Corporation
- Current Assignee: Sandisk Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Davis Wright Tremaine LLP
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
Public/Granted literature
- US20070297234A1 Non-Volatile Memory And Method With Bit Line To Bit Line Coupled Compensation Public/Granted day:2007-12-27
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