公开(公告)号：US08164957B2

公开(公告)日：2012-04-24

申请号：US13178853

申请日：2011-07-08

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/04

CPC classification number: G11C5/146 ,  G11C16/10 ,  G11C16/26 ,  G11C2029/0409

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract translation: 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US07525843B2

公开(公告)日：2009-04-28

申请号：US11618793

申请日：2006-12-30

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/00

CPC classification number: G11C16/28 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/565

Abstract: A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract translation: 可以应用身体偏差以优化性能的非易失性存储系统。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US20080158992A1

公开(公告)日：2008-07-03

申请号：US11618793

申请日：2006-12-30

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/06

CPC classification number: G11C16/28 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/565

Abstract: A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract translation: 可以应用身体偏差以优化性能的非易失性存储系统。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US20110267887A1

公开(公告)日：2011-11-03

申请号：US13178853

申请日：2011-07-08

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/10

CPC classification number: G11C5/146 ,  G11C16/10 ,  G11C16/26 ,  G11C2029/0409

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract translation: 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US20110227020A1

公开(公告)日：2011-09-22

申请号：US13047020

申请日：2011-03-14

Applicant: Deepak Chandra Sekar ,  Franz Kreupl ,  Raghuveer S. Makala

Inventor： Deepak Chandra Sekar ,  Franz Kreupl ,  Raghuveer S. Makala

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1675

Abstract: In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.

Abstract translation: 在第一方面，提供了一种金属绝缘体金属（MIM）堆叠，其包括（1）包含硅 - 锗（SiGe）合金的第一导电层; （2）电阻率切换层，包括形成在所述第一导电层上方的金属氧化物层; 和（3）形成在电阻率切换层上方的第二导电层。 存储单元可以由MIM堆叠形成。 提供了许多其他方面。

公开(公告)号：US08000146B2

公开(公告)日：2011-08-16

申请号：US12759581

申请日：2010-04-13

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/04

CPC classification number: G11C5/146 ,  G11C16/10 ,  G11C16/26 ,  G11C2029/0409

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract translation: 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US07764547B2

公开(公告)日：2010-07-27

申请号：US11961871

申请日：2007-12-20

Applicant: Dana Lee ,  Nima Mokhlesi ,  Deepak Chandra Sekar

Inventor： Dana Lee ,  Nima Mokhlesi ,  Deepak Chandra Sekar

IPC: G11C16/04

CPC classification number: G11C16/30

Abstract: Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.

Abstract translation: 提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。 误差是由电流流动时芯片地线源极电阻的电压降引起的。 为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元 的结构块现在已经跑到地面上了。 变化包括可在聚集节点和地之间连接的非线性电阻元件。

公开(公告)号：US07751244B2

公开(公告)日：2010-07-06

申请号：US12335803

申请日：2008-12-16

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/04

CPC classification number: G11C5/146 ,  G11C16/10 ,  G11C16/26 ,  G11C2029/0409

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract translation: 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US07606072B2

公开(公告)日：2009-10-20

申请号：US11739509

申请日：2007-04-24

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

IPC: G11C16/06

CPC classification number: G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3436

Abstract: A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

Abstract translation: 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。

公开(公告)号：US07583539B2

公开(公告)日：2009-09-01

申请号：US11618786

申请日：2006-12-30

Applicant: Deepak Chandra Sekar ,  Nima Mokhlesi

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/04

CPC classification number: G11C7/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/30

Abstract: A non-volatile storage system in which a body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of the biasing can decrease as temperature increases. The body bias can be applied by applying a voltage to a p-well and n-well of a substrate, applying a voltage to the p-well while grounding the n-well, or grounding the body and applying a voltage to the source and/or drain of a set of non-volatile storage elements. Further, temperature-independent and/or temperature-dependent voltages can be applied to selected and unselected word lines in the non-volatile storage system during program, read or verify operations. The temperature-dependent voltages can vary based on different temperature coefficients.

Abstract translation: 一种非易失性存储系统，其中主体偏置被施加到非易失性存储系统以补偿阈值电压，子阈值斜率，耗尽层宽度和/或1 / f噪声的温度相关变化。 基于温度依赖参考信号设置期望的偏置电平。 在一种方法中，当温度升高时，偏置的水平可以降低。 可以通过向基板的p阱和n阱施加电压来施加主体偏置，在将n阱接地的同时向p阱施加电压，或者接地主体并向源施加电压，并且 /或一组非易失性存储元件的漏极。 此外，在程序，读取或验证操作期间，可以将非依赖于温度的和/或温度依赖的电压施加到非易失性存储系统中的选定和未选择的字线。 温度依赖电压可以根据不同的温度系数而变化。