公开(公告)号：US08126527B2

公开(公告)日：2012-02-28

申请号：US11462283

申请日：2006-08-03

Applicant: David J. Marcinek ,  Kevin Conley ,  Kenneth A. Schenkman

Inventor： David J. Marcinek ,  Kevin Conley ,  Kenneth A. Schenkman

IPC: A61B5/1455

CPC classification number: A61B5/1455 ,  A61B5/0059 ,  A61B5/4519 ,  G01N21/31

Abstract: This document discusses, among other things, quantification of hemoglobin content, and therefore blood volume, of muscle. An analysis of the optical spectra can determine the ratio of hemoglobin (Hb) to myoglobin (Mb) content in intact muscle. The peak position of the in vivo optical spectra from intact tissue is used to determine the ratio of Hb to Mb contributing to the optical signal. The wavelength of the peak is a linear function of the percent contribution of Hb to the optical spectra. Such analysis in combination with known Mb concentrations yields a non-invasive measure of the Hb content for in vivo muscle.

Abstract translation: 本文件除了其他内容外，还讨论了肌肉中血红蛋白含量的定量，因此还讨论了血容量的量化。 光谱的分析可以确定完整肌肉中血红蛋白（Hb）与肌红蛋白（Mb）含量的比例。 来自完整组织的体内光谱的峰位置用于确定对光信号有贡献的Hb与Mb的比率。 峰的波长是Hb对光谱的贡献百分比的线性函数。 结合已知Mb浓度的这种分析产生体内肌肉的Hb含量的非侵入性测量。

公开(公告)号：US20070266295A1

公开(公告)日：2007-11-15

申请号：US11383401

申请日：2006-05-15

Applicant: Kevin Conley

Inventor： Kevin Conley

IPC: G11C29/00

CPC classification number: G11C29/52 ,  G06F11/1068 ,  G11C7/02 ,  G11C7/1006 ,  G11C2029/0409

Abstract: Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be stored but allow correction of large numbers of errors.

Abstract translation: 在存储在非易失性存储器阵列中之前，使用卷积编码对数据进行编码，从而即使存在大量的这种错误也可以校正当读取数据时发生的错误。 小于1的编码速率增加要存储的数据量，但允许校正大量错误。

公开(公告)号：US20070263444A1

公开(公告)日：2007-11-15

申请号：US11383397

申请日：2006-05-15

Applicant: Sergey Gorobets ,  Kevin Conley

Inventor： Sergey Gorobets ,  Kevin Conley

IPC: G11C16/06 ,  G11C11/34

CPC classification number: G11C8/10 ,  G11C16/349 ,  G11C16/3495

Abstract: A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours or days) or as a percentage of estimated initial life. An end of life warning can also be provided. In a particular embodiment, the amount of remaining life (either as a percentage or in real time units) can be based on the average number of erases per block, but augmented by the number of spare blocks or other parameters, so that an end of life warning is given if either the expected amount of remaining life falls below a certain level or the number of spare blocks falls below a safe level.

Abstract translation: 给出了提供关于具有有限寿命的存储器（例如闪存卡）的剩余寿命的信息的系统和方法。 例如，它可以向用户提供实时单位（即，小时或天）中的存储器的预期剩余寿命的量，或作为估计的初始寿命的百分比。 也可以提供生命警告的结束。 在特定实施例中，剩余寿命的量（以百分比或实时单位计）可以基于每个块的平均擦除次数，但是增加了备用块的数量或其他参数，使得结束 如果预期的剩余生命量低于一定水平或备用块数量低于安全水平，则会发出生命警告。

公开(公告)号：US20070180062A1

公开(公告)日：2007-08-02

申请号：US11398841

申请日：2006-04-06

Applicant: Rick Southerland ,  Mark Fears ,  Mark Hershey ,  Chris McCauley ,  Kevin Conley ,  Kevin Hartman ,  Jeremy Gerdes

Inventor： Rick Southerland ,  Mark Fears ,  Mark Hershey ,  Chris McCauley ,  Kevin Conley ,  Kevin Hartman ,  Jeremy Gerdes

IPC: G06F15/16

CPC classification number: H04N21/64322 ,  H04L67/025 ,  H04N21/2187 ,  H04N21/2368 ,  H04N21/4341 ,  H04N21/4622 ,  H04N21/6175

Abstract: A portable media encoder with a remote setup management interface is disclosed. The encoder provides a video input port configured to receive a video input from a video input source, an audio input port configured to receive an audio input from an audio input source, and a digital output port for providing a digital output stream corresponding to the received video input and audio input. An encoding processor converts the video input and the audio input into a streamable digital output format for transmitting through the digital output port, and a digital control input port for receives commands from a remote management computer over the Internet using a web browser and provides the commands to the encoding processor. A housing encloses the processor and provides at least one access panel providing user access to the video input port, the audio input port, the digital output port, and the digital control input port. The housing has a size and configuration that allows the encoder to be hand carried by a single individual.

Abstract translation: 公开了具有远程设置管理接口的便携式媒体编码器。 编码器提供一个视频输入端口，被配置为从视频输入源接收视频输入，配置成从音频输入源接收音频输入的音频输入端口以及用于提供对应于接收到的数字输出流的数字输出端口 视频输入和音频输入。 编码处理器将视频输入和音频输入转换成用于通过数字输出端口传输的可流式数字输出格式，以及数字控制输入端口，用于使用网络浏览器通过因特网从远程管理计算机接收命令，并提供命令 到编码处理器。 壳体包围处理器并且提供至少一个访问面板，其提供对视频输入端口，音频输入端口，数字输出端口和数字控制输入端口的用户访问。 外壳具有允许编码器由单个人手持的尺寸和构造。

公开(公告)号：US20070168564A1

公开(公告)日：2007-07-19

申请号：US11267534

申请日：2005-11-04

Applicant: Kevin Conley ,  E. Thompson

Inventor： Kevin Conley ,  E. Thompson

IPC: G06F3/00

CPC classification number: G06F12/0866 ,  G06F3/0601 ,  G06F12/0804 ,  G06F2003/0694 ,  G06F2212/2022 ,  G06F2212/2146 ,  G06F2212/222 ,  G06F2212/2515 ,  Y02D10/13

Abstract: A memory module is interposed between a host and a disk drive. The memory module includes a solid-state nonvolatile memory used for caching data sent by the host for storage in the disk drive. Caching takes place under the control of a memory controller in the memory module and may be transparent to the host. The disk drive may remain spun-down when data is cached, saving power. The destination for host data may be determined based on desired speed, power consumption and expected need for that data. A host may send specific commands to the memory module to enable additional functions.

Abstract translation: 内存模块插在主机和磁盘驱动器之间。 存储器模块包括用于缓存由主机发送以存储在磁盘驱动器中的数据的固态非易失性存储器。 缓存在存储器模块中的存储器控​​制器的控制下进行，并且可能对主机是透明的。 数据缓存时，磁盘驱动器可能保持静音，节省电力。 可以基于期望的速度，功率消耗和对该数据的预期需要来确定主机数据的目的地。 主机可以向存储器模块发送特定命令以启用附加功能。

公开(公告)号：US20070143833A1

公开(公告)日：2007-06-21

申请号：US11314522

申请日：2005-12-21

Applicant: Kevin Conley

Inventor： Kevin Conley

IPC: H04L9/32

CPC classification number: G06F21/32 ,  G06F21/79

Abstract: A portable memory storage device (“device”) is provided. The device includes a microphone for receiving a user voice input; a controller that receives the voice input and creates a template; and a plurality of non-volatile memory cells for storing the template, wherein the template is used to authenticate the user for any subsequent user request for accessing the device and an application is launched when the device interfaces with a host system to enroll the user as an authorized user to access device functionality and/or access host system functionality.

Abstract translation: 提供了便携式存储器存储设备（“设备”）。 该设备包括用于接收用户语音输入的麦克风; 接收语音输入并创建模板的控制器; 以及用于存储该模板的多个非易失性存储器单元，其中该模板用于对任何用于访问设备的后续用户请求认证用户，并且当该设备与主机系统接口以将该用户注册为 授权用户访问设备功能和/或访问主机系统功能。

公开(公告)号：US20070109858A1

公开(公告)日：2007-05-17

申请号：US11619991

申请日：2007-01-04

Applicant: Kevin Conley ,  Daniel Guterman ,  Carlos Gonzales

Inventor： Kevin Conley ,  Daniel Guterman ,  Carlos Gonzales

IPC: G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2216/14

Abstract: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.

Abstract translation: 改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。 在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。 在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。 当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。 这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。 替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。 可以重复写入后验证，并使用不同的偏置条件读取数据。 该过程可以是自动的，也可以通过可以指定读取条件的命令执行。

公开(公告)号：US20070103978A1

公开(公告)日：2007-05-10

申请号：US11270410

申请日：2005-11-08

Applicant: Kevin Conley ,  Yoram Cedar

Inventor： Kevin Conley ,  Yoram Cedar

IPC: G11C16/06

CPC classification number: G11C29/81 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/808 ,  G11C29/82

Abstract: In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

Abstract translation: 在具有冗余列的存储器阵列中，一种方案允许故障单元被单独地重新映射到冗余列中的冗余单元。 一个冗余列中的冗余单元格可以替换多个非冗余列中的有缺陷单元。 重新映射作为初始测试和配置的一部分完成。 具体硬件可用于方案或固件在内存控制器中可实现的方案。

公开(公告)号：US20070091680A1

公开(公告)日：2007-04-26

申请号：US11611706

申请日：2006-12-15

Applicant: Kevin Conley ,  Yoram Cedar

Inventor： Kevin Conley ,  Yoram Cedar

IPC: G11C16/04

CPC classification number: G11C16/105 ,  G11C16/10 ,  G11C16/102 ,  G11C2216/22

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.

Abstract translation: 本发明允许在非易失性存储器系统中增加编程并行性，而不会引起额外的数据传输等待时间。 数据从控制器传送到第一存储器芯片，并且开始编程操作。 当该第一存储器芯片正在忙于执行该程序操作时，数据从控制器传送到第二存储器芯片，并且使该编程操作在该芯片中开始。 一旦完成编程操作，即使第二个芯片仍在忙于执行其程序操作，数据传输也可以再次开始到第一个存储器芯片。 以这种方式，实现编程操作的高并行性，而不会导致执行附加数据传输的延迟成本。 提出了两组实施例，一种将数据保存在缓冲器中，直到该数据的成功编程得到确认，并且不需要实现成功，并且不保留数据从而实现更高的数据编程吞吐量 。

公开(公告)号：US20070083698A1

公开(公告)日：2007-04-12

申请号：US11539972

申请日：2006-10-10

Applicant: Carlos Gonzalez ,  Kevin Conley

Inventor： Carlos Gonzalez ,  Kevin Conley

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G11C29/76 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495

Abstract: Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.

Abstract translation: 公开了用于在非易失性存储器系统中执行损耗均衡的方法和装置。 包括用于在存储器系统中执行磨损均衡的方法，该存储器系统包括具有包括内容的第一存储器元件的第一区域，并且第二区域包括识别第一存储器元件并将第一存储器元件的内容与第二存储器元件 将第一存储元件的内容与第一区分离。 在一个实施例中，将第一存储器元件的内容与第二存储元件相关联涉及将第二存储器元件的内容移动到第三存储器元件中，然后将第一存储元件的内容复制到第二存储元件中。