公开(公告)号：US12205625B2

公开(公告)日：2025-01-21

申请号：US18245098

申请日：2021-09-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiromichi Godo ,  Yoshiyuki Kurokawa ,  Kazuki Tsuda ,  Satoru Ohshita

IPC: G11C11/22 ,  H01L21/28 ,  H01L29/78 ,  H10B51/30 ,  H10B53/30

Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.

公开(公告)号：US12142693B2

公开(公告)日：2024-11-12

申请号：US17642346

申请日：2020-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Yuichi Yanagisawa ,  Shota Mizukami ,  Kazuki Tsuda ,  Haruyuki Baba ,  Shunpei Yamazaki

IPC: H01L29/786

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor, a second conductor, a third oxide, a fourth oxide, and a second insulator over the second oxide; a third insulator over the first conductor, the second conductor, the third oxide, and the fourth oxide; a fourth insulator over the second insulator; and a third conductor over the fourth insulator. The second insulator is positioned between the first conductor and the second conductor. The third oxide is positioned between the first conductor and the second insulator. The fourth oxide is positioned between the second conductor and the second insulator. The thickness of the third oxide between the first conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm. The thickness of the fourth oxide between the second conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm.

公开(公告)号：US12082391B2

公开(公告)日：2024-09-03

申请号：US17762473

申请日：2020-09-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru Ohshita ,  Hitoshi Kunitake ,  Kazuki Tsuda

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H10B12/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

公开(公告)号：US20220270548A1

公开(公告)日：2022-08-25

申请号：US17671905

申请日：2022-02-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Kouhei Toyotaka ,  Kazuki Tsuda ,  Satoru Ohshita ,  Hidefumi Rikimaru

IPC: G09G3/3225 ,  G02B27/01 ,  H01L27/32 ,  G06F3/01 ,  G09G3/00

Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.

公开(公告)号：US10141544B2

公开(公告)日：2018-11-27

申请号：US15670318

申请日：2017-08-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki Tsuda ,  Kohei Yokoyama ,  Yasuhiro Jinbo

IPC: H01L51/56 ,  G02F1/1368 ,  H01L27/12 ,  H01L51/52 ,  H01L29/66 ,  H01L27/32

Abstract: A highly reliable display device or electronic device is provided. The display device includes a first electrode, a second electrode, a light-emitting layer between the first electrode and the second electrode, and a protective film over the second electrode. The protective film includes a first insulating film and a second insulating film over the first insulating film. The first insulating film includes one or more of aluminum oxide, hafnium oxide, and zirconium oxide, and the second insulating film includes one or more of aluminum oxide, hafnium oxide, and zirconium oxide. A composition of the first insulating film is different from a composition of the second insulating film. A water vapor transmission rate of the protective film is lower than 1×10−2 g/(m2·day).

公开(公告)号：US12206370B2

公开(公告)日：2025-01-21

申请号：US17619669

申请日：2020-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Takayuki Ikeda ,  Kiyoshi Kato ,  Yuichi Yanagisawa ,  Shota Mizukami ,  Kazuki Tsuda

IPC: H03G3/30 ,  H01L29/786 ,  H03F1/02 ,  H03F3/195

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

公开(公告)号：US12200950B2

公开(公告)日：2025-01-14

申请号：US18278199

申请日：2022-02-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi Godo ,  Yoshiyuki Kurokawa ,  Kouhei Toyotaka ,  Kazuki Tsuda ,  Satoru Ohshita ,  Hidefumi Rikimaru

IPC: H10K39/34 ,  G06F3/01 ,  G09G3/3208 ,  H10K59/65

Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user. When the first light-emitting element emits visible light, the light-receiving element has a function of detecting the visible light that is emitted from the first light-emitting element and reflected by the eyeball of the user. The first light-emitting element and the second light-emitting element are placed in one layer. The layer where the first light-emitting element and the second light-emitting element are positioned overlaps with the sensor portion.

公开(公告)号：US11985827B2

公开(公告)日：2024-05-14

申请号：US17790517

申请日：2021-01-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi Godo ,  Hitoshi Kunitake ,  Kazuki Tsuda

IPC: H10B43/27 ,  G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/08 ,  H10B41/27

Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.

公开(公告)号：US12207462B2

公开(公告)日：2025-01-21

申请号：US17776342

申请日：2020-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki Tsuda ,  Hiromichi Godo ,  Satoru Ohshita ,  Hitoshi Kunitake

IPC: H10B41/35 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

公开(公告)号：US12193236B2

公开(公告)日：2025-01-07

申请号：US17772280

申请日：2020-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Satoru Ohshita ,  Kazuki Tsuda ,  Tatsuya Onuki

IPC: H10B43/40 ,  G11C16/08 ,  H10B43/27

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.