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    Sense amplifier architecture for low supply voltage operations
    1.
    发明授权
    Sense amplifier architecture for low supply voltage operations 有权

    公开(公告)号：US11081167B1

    公开(公告)日：2021-08-03

    申请号：US16912716

    申请日：2020-06-26

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Hiroki Yabe ,  Koichiro Hayashi

    IPC分类号： G11C11/4074 ,  G11C11/4091

    摘要： Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.

    WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY
    2.
    发明申请
    WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY 有权

    公开(公告)号：US20210134828A1

    公开(公告)日：2021-05-06

    申请号：US16675800

    申请日：2019-11-06

    申请人： SanDisk Technologies LLC

    发明人： Naoki Ookuma ,  Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Toru Miwa

    IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11573

    摘要： A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

    Word line architecture for three dimensional NAND flash memory
    4.
    发明授权
    Word line architecture for three dimensional NAND flash memory 有权

    公开(公告)号：US11177277B2

    公开(公告)日：2021-11-16

    申请号：US16675800

    申请日：2019-11-06

    申请人： SanDisk Technologies LLC

    发明人： Naoki Ookuma ,  Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Toru Miwa

    IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027

    摘要： A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

    Area effective erase voltage isolation in NAND memory
    8.
    发明授权
    Area effective erase voltage isolation in NAND memory 有权

    公开(公告)号：US10885984B1

    公开(公告)日：2021-01-05

    申请号：US16668073

    申请日：2019-10-30

    申请人： SanDisk Technologies LLC

    发明人： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Yuki Fujita ,  Naoki Ookuma ,  Kazuki Yamauchi ,  Masahito Takehara ,  Toru Miwa

    IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L27/11524

    摘要： A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.