Storage device and storage system

    公开(公告)号:US11586538B2

    公开(公告)日:2023-02-21

    申请号:US17359873

    申请日:2021-06-28

    Abstract: Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.

    Semiconductor Device
    5.
    发明申请
    Semiconductor Device 审中-公开
    半导体器件

    公开(公告)号:US20150228786A1

    公开(公告)日:2015-08-13

    申请号:US14542867

    申请日:2014-11-17

    Abstract: A semiconductor device includes a semiconductor substrate having an active region. A gate trench is disposed to cross the active region. First and second source/drain regions are disposed in the active region at both sides of the gate trench. A gate electrode is disposed in the gate trench. A gate dielectric layer is disposed between the gate electrode and the active region. A stress pattern is disposed on the gate electrode and in the gate trench. The stress pattern has a lower residual stress than silicon nitride.

    Abstract translation: 半导体器件包括具有有源区的半导体衬底。 栅极沟槽被布置成越过有源区域。 第一和第二源极/漏极区域设置在栅极沟槽的两侧的有源区域中。 栅电极设置在栅极沟槽中。 栅电介质层设置在栅电极和有源区之间。 应力图案设置在栅极电极和栅极沟槽中。 应力模式比氮化硅具有更低的残余应力。

    Storage device and storage system

    公开(公告)号:US11080186B2

    公开(公告)日:2021-08-03

    申请号:US16547410

    申请日:2019-08-21

    Abstract: Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.

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