公开(公告)号：US20180155372A1

公开(公告)日：2018-06-07

申请号：US15827317

申请日：2017-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-min RYU ,  Youn-soo KIM ,  Jae-soon LIM ,  Youn-joung CHO ,  Myong-woon KIM ,  Kang-yong LEE ,  Sang-ick LEE ,  Sang-yong JEON

IPC: C07F7/22 ,  C23C16/455

CPC classification number: C07F7/2284 ,  C23C16/407 ,  C23C16/45553

Abstract: A tin compound, tin precursor compound for atomic layer deposition (ALD), a method of forming a tin-containing material film, and a method of synthesizing a tin compound, the tin compound being represented by Chemical Formula (I): wherein R1, R2, Q1, Q2, Q3, and Q4 are each independently a Cl to C4 linear or branched alkyl group.

公开(公告)号：US20210140048A1

公开(公告)日：2021-05-13

申请号：US17153281

申请日：2021-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-min MOON ,  Youn-soo KIM ,  Han-jin LIM ,  Yong-jae LEE ,  Se-hoon OH ,  Hyun-jun KIM ,  Jin-sun LEE

IPC: C23C16/52 ,  H01J37/32 ,  C23C16/455 ,  H01L21/67

Abstract: A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.

公开(公告)号：US20190144472A1

公开(公告)日：2019-05-16

申请号：US16249067

申请日：2019-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-min RYU ,  Youn-soo KIM ,  Jae-soon LIM ,  Youn-joung CHO ,  Myong-woon KIM ,  Kang-yong LEE ,  Sang-ick LEE ,  Sang-yong JEON

IPC: C07F7/22 ,  C23C16/40 ,  C23C16/455

Abstract: A tin compound, tin precursor compound for atomic layer deposition (ALD), a method of forming a tin-containing material film, and a method of synthesizing a tin compound, the tin compound being represented by Chemical Formula (I): wherein R1, R2, Q1, Q2, Q3, and Q4 are each independently a C1 to C4 linear or branched alkyl group.

公开(公告)号：US20170040172A1

公开(公告)日：2017-02-09

申请号：US15227089

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-min MOON ,  Youn-soo KIM ,  Han-jin LIM ,  Yong-jae LEE ,  Se-hoon OH ,  Hyun-jun KIM ,  Jin-sun LEE

IPC: H01L21/28 ,  C23C16/50 ,  H01L29/40 ,  C23C16/455

CPC classification number: H01L21/28008 ,  C23C16/045 ,  C23C16/405 ,  C23C16/4408 ,  C23C16/45534 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/45557 ,  C23C16/45561 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/28282 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/11582 ,  H01L28/40 ,  H01L29/401 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.

Abstract translation: 形成材料层的方法包括将基底提供到反应室中，将源材料提供到基底上，源材料是具有配体的金属或半金属的前体，在基底上提供醚基改性剂，清洗 反应室的内部，并使反应材料与源材料反应以形成材料层。

公开(公告)号：US20190292207A1

公开(公告)日：2019-09-26

申请号：US16439369

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyu-hee PARK ,  Youn-soo KIM ,  Jae-soon LIM ,  Youn-joung CHO ,  Haruyoshi SATO ,  Naoki YAMADA ,  Hiroyuki UCHIUZOU

IPC: C07F7/10

Abstract: A silicon-containing intermediate is synthesized by reacting a lanthanum tris[bis(trialkylsilyl)amide] complex with an alkylcyclopentadiene. A lanthanum compound is synthesized by reacting the silicon-containing intermediate with a dialkylamidine-based compound.

公开(公告)号：US20190152996A1

公开(公告)日：2019-05-23

申请号：US16251236

申请日：2019-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyu-hee PARK ,  Youn-soo KIM ,  Jae-soon LIM ,  Youn-joung CHO ,  Kazuki HARANO ,  Haruyoshi SATO ,  Tsubasa SHIRATORI ,  Naoki YAMADA

IPC: C07F5/00 ,  C23C16/455 ,  C23C16/34 ,  H01L27/28 ,  H01L51/00 ,  H01L51/05

Abstract: A lanthanum compound, a method of synthesizing a thin film, and a method of manufacturing an integrated circuit device, the compound being represented by Formula 1 below, wherein, in Formula 1, R1 is a hydrogen atom or a C1-C4 linear or branched alkyl group, R2 and R3 are each independently a hydrogen atom or a C1-C5 linear or branched alkyl group, at least one of R2 and R3 being a C3-C5 branched alkyl group, and R4 is a hydrogen atom or a C1-C4 linear or branched alkyl group.

公开(公告)号：US20170211183A1

公开(公告)日：2017-07-27

申请号：US15482005

申请日：2017-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-min MOON ,  Youn-soo KIM ,  Han-jin LIM ,  Yong-jae LEE ,  Se-hoon OH ,  Hyun-jun KIM ,  Jin-sun LEE

IPC: C23C16/455 ,  C23C16/44 ,  H01L21/28 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L21/28008 ,  C23C16/045 ,  C23C16/405 ,  C23C16/4408 ,  C23C16/45534 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/45557 ,  C23C16/45561 ,  H01L21/02189 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28194 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/40117 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.

公开(公告)号：US20210273039A1

公开(公告)日：2021-09-02

申请号：US17324492

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-soo KIM ,  Seung-min RYU ,  Chang-su WOO ,  Hyung-suk JUNG ,  Kyu-ho CHO ,  Youn-joung CHO

IPC: H01L49/02 ,  H01L27/108

Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.

公开(公告)号：US20210202693A1

公开(公告)日：2021-07-01

申请号：US17200081

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-goo KANG ,  Sang-yeol KANG ,  Youn-soo KIM ,  Jin-su LEE ,  Hyung-suk JUNG ,  Kyu-ho CHO

IPC: H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L27/108

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

公开(公告)号：US20180342391A1

公开(公告)日：2018-11-29

申请号：US15866568

申请日：2018-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyu-hee PARK ,  Youn-soo KIM ,  Hyun-jun KIM ,  Jin-sun LEE ,  Jae-soon LIM

IPC: H01L21/02 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/108 ,  C23C16/06 ,  C23C16/40 ,  C23C16/02 ,  C23C16/455

CPC classification number: H01L21/02304 ,  C23C16/0272 ,  C23C16/06 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45553 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02356 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/40117

Abstract: A method of forming a thin film and an integrated circuit device, including forming a first reaction inhibiting layer chemisorbed on a first portion of a lower film by supplying a reaction inhibiting compound having a carbonyl group to an exposed surface of the lower film at a temperature of about 300° C. to about 600° C.; forming a first precursor layer of a first material chemisorbed on a second portion of the lower film at a temperature of about 300° C. to about 600° C., the second portion being exposed through the first reaction inhibiting layer; and forming a first monolayer containing the first material on the lower film by supplying a reactive gas to the first reaction inhibiting layer and the first precursor layer and removing the first reaction inhibiting layer from the surface of the lower film, and thus exposing the first portion.