公开(公告)号：US12014957B2

公开(公告)日：2024-06-18

申请号：US17701275

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/3083 ,  H01L21/32139 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US20210082757A1

公开(公告)日：2021-03-18

申请号：US16898906

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US11978775B2

公开(公告)日：2024-05-07

申请号：US17841873

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Hyun-Seung Song ,  Yeongchang Roh ,  Heonjong Shin ,  Sora You ,  Yongsik Jeong

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/45

CPC classification number: H01L29/41775 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/456

Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

公开(公告)号：US20220216107A1

公开(公告)日：2022-07-07

申请号：US17701275

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/28 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/308

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US11309218B2

公开(公告)日：2022-04-19

申请号：US16898906

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/308 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L23/528

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.