公开(公告)号：US11411007B2

公开(公告)日：2022-08-09

申请号：US16991661

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Lee ,  Kiseok Lee ,  Woobin Song ,  Minhee Cho

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

公开(公告)号：US11508851B2

公开(公告)日：2022-11-22

申请号：US17004427

申请日：2020-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Hyunmog Park ,  Minwoo Song ,  Woobin Song ,  Hyunsil Oh ,  Minsu Lee

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/24

Abstract: A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

公开(公告)号：US11482267B2

公开(公告)日：2022-10-25

申请号：US17330828

申请日：2021-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

IPC: G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US11062751B2

公开(公告)日：2021-07-13

申请号：US16704320

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

IPC: G11C11/22 ,  G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US11922984B2

公开(公告)日：2024-03-05

申请号：US17949305

申请日：2022-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

IPC: G11C16/04 ,  G11C11/00 ,  G11C11/22 ,  G11C11/4096 ,  H10B12/00 ,  H10B51/30 ,  H10B51/40

CPC classification number: G11C11/005 ,  G11C11/223 ,  G11C11/2275 ,  G11C11/4096 ,  H10B12/33 ,  H10B12/50 ,  H10B51/30 ,  H10B51/40

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20220384661A1

公开(公告)日：2022-12-01

申请号：US17578893

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Kiseok Lee ,  Wonsok Lee ,  Mintae Ryu ,  Hyunmog Park ,  Woobin Song ,  Sungwon Yoo

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

公开(公告)号：US10916655B2

公开(公告)日：2021-02-09

申请号：US16591958

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woobin Song ,  Heiseung Kim ,  Mirco Cantoro ,  Sangwoo Lee ,  Minhee Cho ,  Beomyong Hwang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/161 ,  H01L21/02 ,  H01L21/28

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

公开(公告)号：US20240096956A1

公开(公告)日：2024-03-21

申请号：US18370663

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjoo Na ,  Woobin Song ,  Jinwook Yang ,  Cheoljin Yun ,  Dongkyu Lee ,  Yoshinao Harada

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4933 ,  H01L29/66553

Abstract: An integrated circuit semiconductor device includes a nanosheet extending above a substrate in a first horizontal direction, a gate electrode extending in a second horizontal direction while surrounding the nanosheet with a gate insulating layer therebetween, a first source/drain region on a side of the nanosheet, and a second source/drain region on another side of the nanosheet, wherein the first source/drain region includes first silicide layers provided inward from surfaces of the nanosheet, first metal layers surrounding the nanosheet from upper and lower sides of the first silicide layers, and a first nanosheet region provided between the first silicide layers, wherein the second source/drain region includes second silicide layers formed inward from the surfaces of the nanosheet, second metal layers surrounding the nanosheet from upper and lower sides of the second silicide layers, and a second nanosheet region provided between the second silicide layers.

公开(公告)号：US11342456B2

公开(公告)日：2022-05-24

申请号：US17144444

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woobin Song ,  Heiseung Kim ,  Mirco Cantoro ,  Sangwoo Lee ,  Minhee Cho ,  Beomyong Hwang

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

公开(公告)号：US20210217897A1

公开(公告)日：2021-07-15

申请号：US17004427

申请日：2020-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Hyunmog Park ,  Minwoo Song ,  Woobin Song ,  Hyunsil Oh ,  Minsu Lee

IPC: H01L29/786 ,  H01L27/12

Abstract: A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.