公开(公告)号：US11157425B2

公开(公告)日：2021-10-26

申请号：US16853807

申请日：2020-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Daeseok Byeon ,  Tongsung Kim

IPC: G06F13/16 ,  G06N3/04 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.

公开(公告)号：US12237046B2

公开(公告)日：2025-02-25

申请号：US17951567

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22

Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

公开(公告)号：US11921664B2

公开(公告)日：2024-03-05

申请号：US18077406

申请日：2022-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Jangwoo Lee ,  Seonkyoo Lee ,  Chiweon Yoon ,  Jeongdon Ihm

IPC: G06F3/06 ,  G06F13/40 ,  G06F18/214

CPC classification number: G06F13/4072 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0679 ,  G06F18/214

Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

公开(公告)号：US20230162766A1

公开(公告)日：2023-05-25

申请号：US17951567

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222

Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

公开(公告)号：US11367471B2

公开(公告)日：2022-06-21

申请号：US17352527

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G11C7/10 ,  H03K19/00 ,  H01L27/115 ,  G11C16/04

Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

公开(公告)号：US20230179193A1

公开(公告)日：2023-06-08

申请号：US17866517

申请日：2022-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

IPC: H03K5/14 ,  H03K5/135 ,  H03L7/081

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

公开(公告)号：US11594287B2

公开(公告)日：2023-02-28

申请号：US17198382

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon

IPC: G11C16/32 ,  G11C16/04 ,  H01L25/065

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

公开(公告)号：US11550498B2

公开(公告)日：2023-01-10

申请号：US17030635

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Jangwoo Lee ,  Seonkyoo Lee ,  Chiweon Yoon ,  Jeongdon Ihm

IPC: G06F3/06 ,  G06K9/62

Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

公开(公告)号：US20220148630A1

公开(公告)日：2022-05-12

申请号：US17352527

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G11C7/10 ,  H03K19/00

Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

公开(公告)号：US11115021B2

公开(公告)日：2021-09-07

申请号：US17021728

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Jungjune Park ,  Jindo Byun ,  Dongho Shin ,  Jeongdon Ihm

IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.