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    Memory system including an interface circuit connecting a controller and memory
    1.
    发明授权
    Memory system including an interface circuit connecting a controller and memory 有权

    公开(公告)号：US12237046B2

    公开(公告)日：2025-02-25

    申请号：US17951567

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22

    Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明公开
    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230162766A1

    公开(公告)日：2023-05-25

    申请号：US17951567

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222

    Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

    MEMORY DEVICE INCLUDING MULTIPLE MEMORY CHIPS AND DATA SIGNAL LINES AND A METHOD OF OPERATING THE MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE INCLUDING MULTIPLE MEMORY CHIPS AND DATA SIGNAL LINES AND A METHOD OF OPERATING THE MEMORY DEVICE 有权

    公开(公告)号：US20220101894A1

    公开(公告)日：2022-03-31

    申请号：US17410210

    申请日：2021-08-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonkyoo Lee ,  Chiweon Yoon ,  Byunghoon Jeong ,  Youngmin Jo

    IPC: G11C7/10 ,  H01L25/065

    Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM
    5.
    发明公开
    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240282378A1

    公开(公告)日：2024-08-22

    申请号：US18444848

    申请日：2024-02-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C16/08 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C16/0483

    Abstract: A memory system includes a memory device having a plurality of non-volatile memories, a buffer chip connected with each of the plurality of non-volatile memories, and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal to the buffer chip. The buffer chip includes a first loop coupled to a sampler circuit and configured to perform first monitoring on the data strobe signal and first duty correction on the data strobe signal based on the first monitoring, and a second loop coupled to a multiplexer and configured to, responsive to the first duty correction, perform second monitoring on the data strobe signal and second duty correction on the data strobe signal based on the second monitoring. The buffer chip is configured to store first and second duty correction information for at least one of the plurality of non-volatile memories.

    Memory device, memory system including memory device and vehicle-based system including memory system
    6.
    发明授权
    Memory device, memory system including memory device and vehicle-based system including memory system 有权

    公开(公告)号：US11157425B2

    公开(公告)日：2021-10-26

    申请号：US16853807

    申请日：2020-04-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngmin Jo ,  Daeseok Byeon ,  Tongsung Kim

    IPC: G06F13/16 ,  G06N3/04 ,  H01L25/065 ,  H01L25/18

    Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.

    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM
    7.
    发明公开
    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240257850A1

    公开(公告)日：2024-08-01

    申请号：US18426825

    申请日：2024-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/225 ,  G11C7/1096 ,  G11C7/222

    Abstract: Provided is a memory system including a memory device including a plurality of non-volatile memories, each of the plurality of non-volatile memories being electrically connected to a buffer chip, and a memory controller electrically connected to the buffer chip and configured to transmit a reference clock signal used in correction of a data signal, wherein the buffer chip includes a delay clock generation chain configured to generate a first delay clock signal or a second delay clock signal from the reference clock signal, a first register configured to store the first delay clock signal, and a second register configured to store the second delay clock signal, and wherein the buffer chip is configured to perform compensation on a strobe signal of the data signal based on the first delay clock signal, and perform compensation on the data signal based on the second delay clock signal.

    MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE
    8.
    发明公开
    MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE 审中-公开

    公开(公告)号：US20230179193A1

    公开(公告)日：2023-06-08

    申请号：US17866517

    申请日：2022-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

    IPC: H03K5/14 ,  H03K5/135 ,  H03L7/081

    CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

    Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

    Nonvolatile memory device and storage device including the nonvolatile memory device
    9.
    发明授权
    Nonvolatile memory device and storage device including the nonvolatile memory device 有权

    公开(公告)号：US11594287B2

    公开(公告)日：2023-02-28

    申请号：US17198382

    申请日：2021-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon

    IPC: G11C16/32 ,  G11C16/04 ,  H01L25/065

    Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

    Memory system and operating method of the same
    10.
    发明授权
    Memory system and operating method of the same 有权

    公开(公告)号：US11289150B2

    公开(公告)日：2022-03-29

    申请号：US17196183

    申请日：2021-03-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngmin Jo ,  Taehyo Kim ,  Daeseok Byeon ,  Seungwon Lee

    IPC: G11C11/40 ,  G11C11/4072 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/4099

    Abstract: A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

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