公开(公告)号：US11100990B2

公开(公告)日：2021-08-24

申请号：US16813826

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Lim ,  Jongryul Kim ,  Taehui Na ,  Venkataramana Gangasani

IPC: G11C11/408 ,  G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

公开(公告)号：US11127457B2

公开(公告)日：2021-09-21

申请号：US16803450

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul Kim ,  Taehui Na ,  Dueung Kim ,  Jongmin Baek

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/408

Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.

公开(公告)号：US11100959B2

公开(公告)日：2021-08-24

申请号：US16560127

申请日：2019-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Rie Sim ,  Taehui Na

IPC: G11C5/06 ,  H01L27/24 ,  G11C5/02 ,  H01L45/00

Abstract: A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines, each word line of the plurality of word lines extending in a second direction intersecting the first direction and arranged in a third direction intersecting the first and second directions, and a memory cell connected to each of the plurality of word lines. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack have a first thickness, in the first direction, of first word lines of the first memory cell stack is less than a second thickness, in the first direction, of each of the plurality of word lines of the second memory cell stack.

公开(公告)号：US10998038B2

公开(公告)日：2021-05-04

申请号：US16797700

申请日：2020-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongryul Kim ,  Taehui Na ,  Dueung Kim ,  Jongmin Baek

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/56 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.

公开(公告)号：US11475948B2

公开(公告)日：2022-10-18

申请号：US16999189

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul Kim ,  Jinyoung Kim ,  Taehui Na

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.

公开(公告)号：US11011228B2

公开(公告)日：2021-05-18

申请号：US16741153

申请日：2020-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung Cho ,  Taehui Na ,  Junho Shin ,  Makoto Hirano

IPC: G11C13/00

Abstract: A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.

公开(公告)号：US20210027829A1

公开(公告)日：2021-01-28

申请号：US16797700

申请日：2020-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul Kim ,  Taehui Na ,  Dueung Kim ,  Jongmin Baek

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/56

Abstract: A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.