公开(公告)号：US20210027829A1

公开(公告)日：2021-01-28

申请号：US16797700

申请日：2020-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul Kim ,  Taehui Na ,  Dueung Kim ,  Jongmin Baek

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/56

Abstract: A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.

公开(公告)号：US11244721B2

公开(公告)日：2022-02-08

申请号：US16821265

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dojeon Lee ,  Dueung Kim ,  Jin-Young Kim

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.

公开(公告)号：US10985213B2

公开(公告)日：2021-04-20

申请号：US16780014

申请日：2020-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Si-Ho Song ,  Youngbae Kim ,  Dueung Kim ,  Changhyun Cho

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: A nonvolatile memory device includes a memory cell array, a word line drive block that is connected to a first group of memory cells through a first group of word lines and to a second group of memory cells through a second group of word lines, a bit line bias and sense block that is connected to the first and second groups of memory cells through bit lines, a variable current supply block that generates a word line current to be supplied to a selected word line, and a control logic block that receives an address and a command and controls the variable current supply block to adjust an amount of the word line current based on the address. The control logic block further varies the amount of the word line current depending on a distance between the selected word line and the substrate.

公开(公告)号：US11127457B2

公开(公告)日：2021-09-21

申请号：US16803450

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul Kim ,  Taehui Na ,  Dueung Kim ,  Jongmin Baek

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/408

Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.

公开(公告)号：US10998038B2

公开(公告)日：2021-05-04

申请号：US16797700

申请日：2020-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongryul Kim ,  Taehui Na ,  Dueung Kim ,  Jongmin Baek

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/56 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.