公开(公告)号：US09806204B2

公开(公告)日：2017-10-31

申请号：US14536250

申请日：2014-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Soo Ahn ,  O Ik Kwon ,  Bum-Soo Kim ,  Hyun-Sung Kim ,  Kyoung-Sub Shin ,  Min-Kyung Yun ,  Seung-Pil Chung ,  Won-Bong Jung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L27/11521 ,  H01L29/423

CPC classification number: H01L29/7883 ,  H01L21/7682 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

公开(公告)号：US11145671B2

公开(公告)日：2021-10-12

申请号：US16511698

申请日：2019-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haejoon Lee ,  Sung-Soo Ahn ,  Ha-Na Kim

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L23/522 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A three-dimensional semiconductor memory device is provided. The memory device includes a substrate with a cell array region and a connection region adjacent to the cell array region, the connection region including a first pad region and a second pad region; an electrode structure including electrodes stacked on the substrate, the electrode structure including an upper portion forming an upper staircase structure; a first dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the first pad region; and a second dummy structure laterally spaced apart from the upper portion of the electrode structure and provided on the second pad region. Each of the first dummy structure and the second dummy structure includes a dummy staircase structure, and the first dummy structure is located at higher level than the second dummy structure.

公开(公告)号：US11109812B2

公开(公告)日：2021-09-07

申请号：US16212946

申请日：2018-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Korea Advanced Institute of Science and Technology

Inventor： Chisung Bae ,  Jin Woo Shin ,  Sung-Soo Ahn ,  Sang Joon Kim

IPC: A61B5/117 ,  A61B5/00 ,  G06F21/32 ,  A61B5/349 ,  G06K9/00

Abstract: An authentication apparatus includes one or more processors configured to temporally implement a neural network, used to extract a feature value from hidden nodes, that is connected to input nodes to which an electrocardiogram (ECG) signal is input so as to share a weight set with the input nodes, and to match the ECG signal and the extracted feature value to a user for registration.

公开(公告)号：US10971516B2

公开(公告)日：2021-04-06

申请号：US16294425

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Ahn ,  Yong-Hoon Son ,  Minhyuk Kim ,  Jae Ho Min ,  Daehyun Jang

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/1157

Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.

公开(公告)号：US10188351B2

公开(公告)日：2019-01-29

申请号：US15246712

申请日：2016-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Korea Advanced Institute of Science and Technology

Inventor： Chisung Bae ,  Jin Woo Shin ,  Sung-Soo Ahn ,  Sang Joon Kim

IPC: A61B5/117 ,  A61B5/00 ,  A61B5/0452 ,  G06F21/32 ,  G06K9/00

Abstract: An authentication apparatus includes one or more processors configured to temporally implement a neural network, used to extract a feature value from hidden nodes, that is connected to input nodes to which an electrocardiogram (ECG) signal is input so as to share a weight set with the input nodes, and to match the ECG signal and the extracted feature value to a user for registration.