公开(公告)号：US12046650B2

公开(公告)日：2024-07-23

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US20240282835A1

公开(公告)日：2024-08-22

申请号：US18649646

申请日：2024-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun Kim ,  Hyung Jong Lee ,  Seulgi Yun ,  Seki Hong

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

公开(公告)号：US11978779B2

公开(公告)日：2024-05-07

申请号：US17580847

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun Kim ,  Hyung Jong Lee ,  Seulgi Yun ,  Seki Hong

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

公开(公告)号：US20240282834A1

公开(公告)日：2024-08-22

申请号：US18649553

申请日：2024-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun Kim ,  Hyung Jong Lee ,  Seulgi Yun ,  Seki Hong

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

公开(公告)号：US11380686B2

公开(公告)日：2022-07-05

申请号：US17101472

申请日：2020-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Seulgi Yun ,  Seki Hong

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes first and second transistors on a substrate. The first transistor includes a first N-type active region, a first gate electrode having a first work function layer, and a first gate dielectric layer having high-k dielectrics containing La. The first work function layer includes a first layer having TiON, a second layer having TiN or TiON, a third layer having TiON, a fourth layer having TiN, and a fifth layer having TiAlC. The second transistor includes a first P-type active region, a second gate electrode having a second work function layer, and a second gate dielectric layer having high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer.

公开(公告)号：US20210328035A1

公开(公告)日：2021-10-21

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US20240339514A1

公开(公告)日：2024-10-10

申请号：US18743588

申请日：2024-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US11901358B2

公开(公告)日：2024-02-13

申请号：US17497449

申请日：2021-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsoo Seo ,  Sangjung Kang ,  Juyoun Kim ,  Seulgi Yun ,  Seki Hong

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure on a substrate, partially removing the dummy gate structure to form a first opening that divides the dummy gate structure, forming a first division pattern structure in the first opening, replacing the dummy gate structure with a gate structure, removing the first division pattern structure to form a second opening, removing a portion of the gate structure from a sidewall of the second opening to enlarge the second opening, and forming a second division pattern in the enlarged second opening.

公开(公告)号：US11575018B2

公开(公告)日：2023-02-07

申请号：US17153464

申请日：2021-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Junmo Park ,  Seulgi Yun

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

公开(公告)号：US20210328038A1

公开(公告)日：2021-10-21

申请号：US17153464

申请日：2021-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Junmo Park ,  Seulgi Yun

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.