公开(公告)号：US20210328035A1

公开(公告)日：2021-10-21

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US20250120114A1

公开(公告)日：2025-04-10

申请号：US18663238

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolsoon Jeong ,  Sangjung Kang ,  Jido Ryu ,  Hwasung Rhee ,  Hochul Lim

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit semiconductor device includes an active fin on a substrate, gate structures apart from one another on the active fin, an interlayer insulation layer to insulate the gate structures on the active fin, gate contacts apart from one another on the gate structures, active contacts apart from one another at both sides of the gate structures, the active contacts passing through the interlayer insulation layer and contacting the active fin, an etch stopping layer on the gate structures, the interlayer insulation layer, the gate contacts, and the active contacts, and diffusion break regions between the active contacts, the diffusion break regions being buried in gate trenches passing through the etch stopping layer and the interlayer insulation layer and in fin recesses cutting the active fin under the gate trenches.

公开(公告)号：US12046650B2

公开(公告)日：2024-07-23

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US20240339514A1

公开(公告)日：2024-10-10

申请号：US18743588

申请日：2024-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US11901358B2

公开(公告)日：2024-02-13

申请号：US17497449

申请日：2021-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsoo Seo ,  Sangjung Kang ,  Juyoun Kim ,  Seulgi Yun ,  Seki Hong

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure on a substrate, partially removing the dummy gate structure to form a first opening that divides the dummy gate structure, forming a first division pattern structure in the first opening, replacing the dummy gate structure with a gate structure, removing the first division pattern structure to form a second opening, removing a portion of the gate structure from a sidewall of the second opening to enlarge the second opening, and forming a second division pattern in the enlarged second opening.

公开(公告)号：US11575018B2

公开(公告)日：2023-02-07

申请号：US17153464

申请日：2021-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Junmo Park ,  Seulgi Yun

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

公开(公告)号：US20210328038A1

公开(公告)日：2021-10-21

申请号：US17153464

申请日：2021-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Junmo Park ,  Seulgi Yun

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.