公开(公告)号：US20210328035A1

公开(公告)日：2021-10-21

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US20240339514A1

公开(公告)日：2024-10-10

申请号：US18743588

申请日：2024-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US12046650B2

公开(公告)日：2024-07-23

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.