公开(公告)号：US20140299944A1

公开(公告)日：2014-10-09

申请号：US14244223

申请日：2014-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-jong CHUNG ,  David SEO ,  Seong-jun PARK ,  Kyung-eun BYUN ,  Hyun-jae SONG ,  Hee-jun YANG ,  Jin-seong HEO

IPC: H01L29/47 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/47 ,  B82Y10/00 ,  H01L21/74 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1606 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7781 ,  H01L29/7839

Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate.

Abstract translation: 石墨烯装置包括：具有第一区域和第二区域的半导体衬底; 在第一区域上但不在半导体衬底的第二区域上的石墨烯层; 在所述石墨烯层的第一部分上的第一电极; 在所述石墨烯层的第二部分上的第二电极; 石墨烯层和第二电极之间的绝缘层; 以及在所述半导体衬底的第二区域上的第三电极。 半导体衬底具有由第一电极，石墨烯层和半导体衬底的结合形成的可调肖特基势垒。

公开(公告)号：US20140158989A1

公开(公告)日：2014-06-12

申请号：US14103079

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-eun BYUN ,  Seong-jun PARK ,  David SEO ,  Hyun-jae SONG ,  Jae-ho LEE ,  Hyun-jong CHUNG ,  Jin-seong HEO

IPC: H01L29/16 ,  H01L29/775

CPC classification number: H01L29/1606 ,  H01L29/1087 ,  H01L29/45 ,  H01L29/452 ,  H01L29/456 ,  H01L29/458 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/78618

Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm−3, and a depletion width of less than or equal to 3 nm.

Abstract translation: 根据示例性实施例，电子设备包括：半导体层; 直接接触所述半导体层的期望（和/或备选地预定）区域的石墨烯; 和石墨烯上的金属层。 半导体层的期望（和/或备选地）预定区域包括以下之一：恒定的掺杂密度，等于或小于1019cm-3的掺杂密度以及小于或等于3nm的耗尽宽度 。

公开(公告)号：US20140014905A1

公开(公告)日：2014-01-16

申请号：US13772693

申请日：2013-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Jae-ho LEE ,  Seong-jun PARK ,  Kyung-eun BYUN ,  David SEO ,  Hyun-jae SONG ,  Hyung-cheol SHIN ,  Jae-hong LEE ,  Hyun-jong CHUNG ,  Jin-seong HEO

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/1095 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/78684 ,  Y10S977/734 ,  Y10S977/842 ,  Y10S977/938

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract translation: 根据示例性实施例，场效应晶体管包括在衬底上的石墨烯通道层。 石墨烯通道层限定狭缝。 源电极和漏极彼此间隔开并布置成向石墨烯通道层施加电压。 栅极绝缘层在石墨烯沟道层和栅电极之间。

公开(公告)号：US20130175506A1

公开(公告)日：2013-07-11

申请号：US13733304

申请日：2013-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-seong HEO ,  Seong-jun PARK ,  Kyung-eun BYUN ,  David SEO ,  Hyun-jae SONG ,  Hee-jun YANG ,  Hyun-jong CHUNG

IPC: H01L29/786

CPC classification number: H01L29/78684 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Abstract translation: 开关器件包括在第一电极和形成在衬底上的第二电极之间的三维堆叠结构中形成的半导体层，石墨烯层，栅极绝缘层和栅极。

公开(公告)号：US20150194234A1

公开(公告)日：2015-07-09

申请号：US14337741

申请日：2014-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-jin SHIN ,  Seong-jun PARK ,  Jae-ho LEE ,  Seong-Jun JEONG

IPC: H01B1/08 ,  C23C16/455 ,  C23C16/06 ,  C23C14/24 ,  C23C14/08 ,  C23C14/14 ,  H01B1/02 ,  C23C16/44

CPC classification number: H01B1/08 ,  C23C14/025 ,  C23C14/08 ,  C23C16/0281 ,  C23C16/40 ,  Y10T428/265

Abstract: A thin film structure includes a metal seed layer, and a method of forming an oxide thin film on a conductive substrate by using the metal seed layer is disclosed. The thin film structure includes a transparent conductive substrate, a metal seed layer that is deposited on the transparent conductive substrate, and a metal oxide layer that is deposited on the metal seed layer.

Abstract translation: 公开了一种薄膜结构，包括金属种子层，以及通过使用金属种子层在导电性基板上形成氧化物薄膜的方法。 薄膜结构包括透明导电基板，沉积在透明导电基板上的金属籽晶层和沉积在金属籽晶层上的金属氧化物层。

公开(公告)号：US20150137075A1

公开(公告)日：2015-05-21

申请号：US14265769

申请日：2014-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-seong HEO ,  Seong-jun PARK ,  Hyeon-jin SHIN

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/24

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/242 ,  H01L29/267 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/7827

Abstract: Inverters including two-dimensional (2D) material, methods of manufacturing the same, and logic devices including the inverters. An inverter may include a first transistor and a second transistor that are connected to each other, and the first and second transistor layers may include 2D materials. The first transistor may include a first graphene layer and a first 2D semiconductor layer contacting the first graphene layer, and the second transistor may include a second graphene layer and a second 2D semiconductor layer contacting the second graphene layer. The first 2D semiconductor layer may be a p-type semiconductor, and the second 2D semiconductor layer may be an n-type semiconductor. The first 2D semiconductor layer may be arranged at a lateral side of the second 2D semiconductor layer.

Abstract translation: 包括二维（2D）材料的逆变器，其制造方法以及包括逆变器的逻辑器件。 反相器可以包括彼此连接的第一晶体管和第二晶体管，并且第一和第二晶体管层可以包括2D材料。 第一晶体管可以包括第一石墨烯层和与第一石墨烯层接触的第一2D半导体层，并且第二晶体管可以包括第二石墨烯层和与第二石墨烯层接触的第二2D半导体层。 第一2D半导体层可以是p型半导体，第二2D半导体层可以是n型半导体。 第一2D半导体层可以布置在第二2D半导体层的侧面。

公开(公告)号：US20150194233A1

公开(公告)日：2015-07-09

申请号：US14588734

申请日：2015-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-jun JEONG ,  Seong-jun PARK ,  Hyeon-jin SHIN ,  Yea-hyun GU ,  Hyoung-sub KIM ,  Jae-hyun YANG

IPC: H01B1/04 ,  H01B13/06 ,  C23C16/02 ,  C23C16/455 ,  H01L29/16 ,  C23C16/06

CPC classification number: H01B1/04 ,  C23C16/0281 ,  C23C16/40 ,  C23C16/405 ,  C23C16/45553 ,  H01L29/1606 ,  H01L29/513 ,  H01L29/7781 ,  Y10T428/265 ,  Y10T428/30

Abstract: Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.

Abstract translation: 示例性实施例涉及具有在石墨烯层上形成的材料层的堆叠结构，以及在石墨烯层上形成材料层的方法。 在堆叠结构中，当通过使用ALD方法在石墨烯层上形成材料层时，可以通过使用线型前体在石墨烯层上形成作为种子层的中间层。

公开(公告)号：US20150155287A1

公开(公告)日：2015-06-04

申请号：US14265965

申请日：2014-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-seong HEO ,  Seong-jun PARK ,  Hyeon-jin SHIN ,  Jae-ho LEE

IPC: H01L27/115 ,  H01L29/43 ,  H01L29/51 ,  H01L29/16

CPC classification number: H01L29/1606 ,  G11C13/0014 ,  G11C13/025 ,  G11C2213/35 ,  H01L27/10808 ,  H01L27/10873 ,  H01L29/66015 ,  H01L29/7606 ,  H01L45/149

Abstract: Disclosed are memory devices including a two-dimensional (2D) material, methods of manufacturing the same, and methods of operating the same. A memory device may include a transistor, which includes graphene and 2D semiconductor contacting the graphene, and a capacitor connected to the transistor. The memory device may include a first electrode, a first insulation layer, a second electrode, a semiconductor layer, a third electrode, a second insulation layer, and a fourth electrode which are sequentially arranged. The second electrode may include the graphene, and the semiconductor layer may include the 2D semiconductor. Alternatively, the memory device may include first and second electrode elements, a graphene layer between the first and second electrode elements, a 2D semiconductor layer between the graphene layer and the first electrode element, and a dielectric layer between the graphene layer and the second electrode.

Abstract translation: 公开了包括二维（2D）材料，其制造方法及其操作方法的存储器件。 存储器件可以包括晶体管，其包括与石墨烯接触的石墨烯和2D半导体以及连接到晶体管的电容器。 存储器件可以包括依次布置的第一电极，第一绝缘层，第二电极，半导体层，第三电极，第二绝缘层和第四电极。 第二电极可以包括石墨烯，并且半导体层可以包括2D半导体。 或者，存储器件可以包括第一和第二电极元件，在第一和第二电极元件之间的石墨烯层，在石墨烯层和第一电极元件之间的2D半导体层，以及在石墨烯层和第二电极之间的电介质层 。

公开(公告)号：US20150137074A1

公开(公告)日：2015-05-21

申请号：US14334028

申请日：2014-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-ho LEE ,  Kyung-eun BYUN ,  Hyun-jae SONG ,  Hyeon-jin SHIN ,  Min-Hyun LEE ,  In-kyeong YOO ,  Seong-jun PARK

IPC: H01L29/66 ,  H01L29/267 ,  H01L29/165 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66977 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42364 ,  H01L29/66045 ,  H01L29/778 ,  H01L29/78

Abstract: A graphene device including separated junction contacts and a method of manufacturing the same are disclosed. The graphene device is a field effect transistor (FET) in which graphene is used as a channel. A source electrode and a drain electrode do not directly contact the graphene channel, and junction contacts formed by doping semiconductor are separately disposed between the graphene channel and the source electrode and between the graphene channel and the drain electrode. Therefore, in an off state where a voltage is not applied to a gate electrode, due to a barrier between the graphene channel and the junction contacts, carriers may not move. As a result, the graphene device may have low current in the off state.

Abstract translation: 公开了一种包括分离的接点的石墨烯器件及其制造方法。 石墨烯装置是其中使用石墨烯作为通道的场效应晶体管（FET）。 源电极和漏电极不直接接触石墨烯通道，并且由掺杂半导体形成的结接点分别设置在石墨烯通道和源电极之间以及石墨烯通道和漏电极之间。 因此，在由于石墨烯通道和接合点之间的阻挡而不向栅电极施加电压的关闭状态下，载体可能不移动。 结果，石墨烯器件在断开状态下可能具有低电流。

公开(公告)号：US20140231752A1

公开(公告)日：2014-08-21

申请号：US14180928

申请日：2014-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-jin SHIN ,  Kyung-eun BYUN ,  Hyun-jae SONG ,  Seong-jun PARK ,  David SEO ,  Yun-sung WOO ,  Dong-wook LEE ,  Jae-ho LEE ,  Hyun-jong CHUNG ,  Jin-seong HEO ,  In-kyeong YOO

IPC: H01L29/16 ,  H01L33/34 ,  H01L31/028 ,  H01L29/786

CPC classification number: H01L29/1606 ,  H01L29/786 ,  H01L29/78642 ,  H01L29/78684 ,  H01L31/028 ,  H01L31/08 ,  H01L33/34 ,  H01L51/0046 ,  H01L51/0504 ,  H01L51/0558 ,  H01L51/0562 ,  H01L51/0566 ,  H01L51/057 ,  H01L51/428 ,  H01L51/50

Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Abstract translation: 提供了石墨烯装置和包括该石墨烯装置的电子装置。 根据示例性实施例，石墨烯装置包括晶体管，其包括源极，栅极和漏极，载流子移动的有源层以及栅极和有源层之间的石墨烯层。 石墨烯层可以被配置为既用作有源层的电极和晶体管的沟道层。