公开(公告)号：US10804158B2

公开(公告)日：2020-10-13

申请号：US16785236

申请日：2020-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namgyu Cho ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

IPC: H01L21/82 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

公开(公告)号：US20200176317A1

公开(公告)日：2020-06-04

申请号：US16785236

申请日：2020-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namgyu CHO ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

IPC: H01L21/8234 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

公开(公告)号：US11901356B2

公开(公告)日：2024-02-13

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungha Oh ,  Pil-Kyu Kang ,  Kughwan Kim ,  Weonhong Kim ,  Yuichiro Sasaki ,  Sang Woo Lee ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L27/06 ,  H01L23/48 ,  H10B41/60 ,  H10B43/20 ,  H10B63/00

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H10B41/60 ,  H10B43/20 ,  H10B63/30 ,  H10B63/84

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

公开(公告)号：US11177286B2

公开(公告)日：2021-11-16

申请号：US16807410

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/762 ,  H01L27/02

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US11728347B2

公开(公告)日：2023-08-15

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/76224 ,  H01L27/0203 ,  H01L27/02 ,  H01L29/78

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US10593597B2

公开(公告)日：2020-03-17

申请号：US16185213

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namgyu Cho ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

IPC: H01L21/82 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.