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Patent Agency Ranking
公开(公告)号：US11961564B2
公开(公告)日：2024-04-16
申请号：US17503952
申请日：2021-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang-Yeon Yu , Kui-Han Ko , Il-Han Park , June-Hong Park , Joo-Yong Park , Joon-Young Park , Bong-Soon Lim
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/0483
Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
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公开(公告)号：US11664361B2
公开(公告)日：2023-05-30
申请号：US17577647
申请日：2022-01-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho Kim , Joo-Yong Park , Daeseok Byeon
CPC classification number: H01L25/18 , H01L24/08 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.
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公开(公告)号：US11233042B2
公开(公告)日：2022-01-25
申请号：US16850493
申请日：2020-04-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho Kim , Joo-Yong Park , Daeseok Byeon
IPC: H01L25/18 , H01L27/11573 , H01L23/528 , H01L23/522 , H01L27/11582 , H01L49/02 , H01L27/11565 , H01L23/00 , H01L27/11575
Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.
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公开(公告)号：US11183249B2
公开(公告)日：2021-11-23
申请号：US16141147
申请日：2018-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang-Yeon Yu , Kui-Han Ko , Il-Han Park , June-Hong Park , Joo-Yong Park , Joon-Young Park , Bong-Soon Lim
IPC: G11C16/16 , G11C16/08 , G11C16/26 , G11C16/04 , G11C16/24 , G11C11/56 , G11C16/10 , H01L27/11556 , H01L27/1157 , H01L27/11582
Abstract: To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
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公开(公告)号：US11233043B2
公开(公告)日：2022-01-25
申请号：US17002149
申请日：2020-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho Kim , Joo-Yong Park , Daeseok Byeon
Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.
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