公开(公告)号：US11233068B2

公开(公告)日：2022-01-25

申请号：US17193187

申请日：2021-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US10672791B2

公开(公告)日：2020-06-02

申请号：US16200714

申请日：2018-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US11211403B2

公开(公告)日：2021-12-28

申请号：US17073653

申请日：2020-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  G11C16/04

Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.

公开(公告)号：US10978481B2

公开(公告)日：2021-04-13

申请号：US16861939

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US10692578B2

公开(公告)日：2020-06-23

申请号：US15955029

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-chang Jeon ,  Kui-han Ko ,  Dong-hun Kwak ,  Jin-young Kim

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F13/00 ,  G06F13/16 ,  G11C16/30 ,  G11C16/32 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/04 ,  G11C7/10 ,  G11C5/14

Abstract: Provided is a method performed by a nonvolatile memory device, the method may include: initiating a first program operation corresponding to a first program loop among a plurality of program loops; receiving a suspend command for an urgent read operation during the first program operation; determining a recovery timing from either of a first timing contemporaneous with the receiving the suspend command, and a second timing after completion of the first program operation, based on the suspend command; and initiating a recovery at the determined recovery timing by applying a recovery voltage to a selected word line.

公开(公告)号：US20190057742A1

公开(公告)日：2019-02-21

申请号：US15955029

申请日：2018-04-17

Applicant: Samsung Electronics Co, Ltd

Inventor： Su-chang JEON ,  Kui-han Ko ,  Dong-hun Kwak ,  Jin-young Kim

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04 ,  H01L27/11582

Abstract: Provided is a method performed by a nonvolatile memory device, the method may include: initiating a first program operation corresponding to a first program loop among a plurality of program loops; receiving a suspend command for an urgent read operation during the first program operation; determining a recovery timing from either of a first timing contemporaneous with the receiving the suspend command, and a second timing after completion of the first program operation, based on the suspend command; and initiating a recovery at the determined recovery timing by applying a recovery voltage to a selected word line.