公开(公告)号：US12176262B2

公开(公告)日：2024-12-24

申请号：US18475926

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/18

Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

公开(公告)号：US11798862B2

公开(公告)日：2023-10-24

申请号：US17354291

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1616 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/30111

Abstract: A semiconductor package includes a base substrate including a wiring pattern, an interposer substrate including lower and upper redistribution patterns, a semiconductor structure, a heat dissipation structure, a plurality of external connection bumps disposed on a lower surface of the base substrate, a plurality of lower connection bumps disposed between the base substrate and the interposer substrate, and a plurality of upper connection bumps disposed between the interposer substrate and the semiconductor structure.

公开(公告)号：US11121069B2

公开(公告)日：2021-09-14

申请号：US16580480

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Choi ,  Doohwan Lee ,  Byungho Kim ,  Jooyoung Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip including a connection pad disposed on an active surface of the semiconductor chip, a passivation layer disposed on the connection pad and the active surface and having an opening exposing at least a portion of the connection pad, and a capping pad covering the connection pad exposed to the opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a connection via connected to the capping pad and a redistribution layer connected to the connection via, wherein the capping pad includes: a central portion disposed in the opening, and a peripheral portion extending from the central portion onto the passivation layer, and having a crystal grain having a size different from that of the crystal grain of the central portion.

公开(公告)号：US10410974B2

公开(公告)日：2019-09-10

申请号：US16195293

申请日：2018-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Gug Min ,  Sungil Cho ,  Jaehoon Choi ,  Shi-kyung Kim

IPC: H01L23/552 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a semiconductor chip provided on the substrate, and a molding layer provided on the substrate and covering the semiconductor chip, the substrate including a ground pattern exposed at one surface of the substrate; and applying a solution including metal particles and a conductive carbon material onto the molding layer to form a shielding layer covering the molding layer. The shielding layer includes the metal particles and the conductive carbon material connected to at least one of the metal particles. The shielding layer extends onto the one surface of the substrate and is electrically connected to the ground pattern.

公开(公告)号：US20240051859A1

公开(公告)日：2024-02-15

申请号：US18200615

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongkeun Yi ,  Jehun Kim ,  Suhyoung Cho ,  Jiwon Chun ,  Junyul Hur ,  Jaedong Hwang ,  Daesoo Park ,  Jaehyung Park ,  Seungjoon Chung ,  Yongxun Jin ,  Jaehoon Choi ,  Seokhwan Hong

IPC: C02F9/00 ,  C02F1/52

CPC classification number: C02F9/00 ,  C02F1/5209 ,  C02F2101/14

Abstract: An apparatus for treating waste water including: a first flocculation tank to which a first flocculant is provided to produce a first flocculated material in which fluorine in waste water introduced from a waste water storage part is coagulated; a second flocculation tank to which a second flocculant and carbon dioxide are provided to produce a second flocculated material in which the first flocculated material and residual fluorine in first outflow water introduced from the first flocculation tank are flocculated; a third flocculation tank to which a third flocculant is provided to produce a third flocculated material in which the first flocculated material and the second flocculated material in second outflow water introduced from the second flocculation tank are flocculated; a first sedimentation tank in which third outflow water introduced from the third flocculation tank is solid-liquid separated into first sludge containing the third flocculated material and first supernatant water; a nitrification tank in which alkalinity is provided by a carbonate supplied from the carbon dioxide, and ammoniacal nitrogen in the first supernatant water introduced from the first sedimentation tank is oxidized by nitrifying microorganisms; and a second sedimentation tank in which fourth outflow water introduced from the nitrification tank is solid-liquid separated into second sludge and second supernatant water.

公开(公告)号：US20240030089A1

公开(公告)日：2024-01-25

申请号：US18475926

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/563 ,  H01L24/16 ,  H01L25/18 ,  H01L25/0655 ,  H01L23/3185 ,  H01L2924/3025 ,  H01L2224/16227 ,  H01L2924/1616 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/30111

Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

公开(公告)号：US11646241B2

公开(公告)日：2023-05-09

申请号：US16720131

申请日：2019-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Choi ,  Sayoon Kang ,  Taewook Kim ,  Hwasub Oh ,  Jooyoung Choi

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/00 ,  H01L23/28 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/34 ,  H01L23/28 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

公开(公告)号：US20200273771A1

公开(公告)日：2020-08-27

申请号：US16720131

申请日：2019-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Choi ,  Sayoon Kang ,  Taewook Kim ,  Hwasub Oh ,  Jooyoung Choi

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/28 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

公开(公告)号：US20200152565A1

公开(公告)日：2020-05-14

申请号：US16580480

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Choi ,  Doohwan Lee ,  Byungho Kim ,  Jooyoung Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip including a connection pad disposed on an active surface of the semiconductor chip, a passivation layer disposed on the connection pad and the active surface and having an opening exposing at least a portion of the connection pad, and a capping pad covering the connection pad exposed to the opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a connection via connected to the capping pad and a redistribution layer connected to the connection via, wherein the capping pad includes: a central portion disposed in the opening, and a peripheral portion extending from the central portion onto the passivation layer, and having a crystal grain having a size different from that of the crystal grain of the central portion.

公开(公告)号：US20190109095A1

公开(公告)日：2019-04-11

申请号：US16195293

申请日：2018-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Gug Min ,  Sungil Cho ,  Jaehoon Choi ,  Shi-kyung Kim

IPC: H01L23/552 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a semiconductor chip provided on the substrate, and a molding layer provided on the substrate and covering the semiconductor chip, the substrate including a ground pattern exposed at one surface of the substrate; and applying a solution including metal particles and a conductive carbon material onto the molding layer to form a shielding layer covering the molding layer. The shielding layer includes the metal particles and the conductive carbon material connected to at least one of the metal particles. The shielding layer extends onto the one surface of the substrate and is electrically connected to the ground pattern.