公开(公告)号：US20230301068A1

公开(公告)日：2023-09-21

申请号：US18118766

申请日：2023-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanchul JEON ,  Yeonsu KIM ,  Youngsik LEE ,  Hyuk KIM ,  Sangwuk PARK

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/5283 ,  H10B12/05

Abstract: A semiconductor memory device includes a substrate, contact electrodes extending in a first direction, each of the contact electrodes including a connection portion having a first thickness and a landing portion having a second thickness, an uppermost contact electrode above the contact electrodes, the contact electrodes being longer in the first direction than the uppermost contact electrode and defining a step structure, transistor bodies extending in a second direction and having a first source/drain, a monocrystalline channel layer, and a second source/drain sequentially arranged in the second direction, the monocrystalline channel layer being connected to a corresponding contact electrode, a lower electrode layer connected to the second source/drain of each of the transistor bodies, a capacitor dielectric layer covering the lower electrode layer and having a uniform thickness, and an upper electrode layer separated from the lower electrode layer by the capacitor dielectric layer.

公开(公告)号：US20230209826A1

公开(公告)日：2023-06-29

申请号：US18080325

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongeun YOOK ,  Hyuk KIM ,  Youngsik LEE

IPC: H10B43/27 ,  H01L23/535 ,  H10B43/40

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first region and a second region, the second region extending from the first region; a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, the stack having a staircase structure on the second region; an insulating layer covering the staircase structure of the stack; first vertical channel structures on the first region, penetrating the stack, and in contact with the substrate; first contact plugs on the second region and penetrating the insulating layer and the stack; and first insulating pads in the insulating layer and enclosing upper portions of the first contact plugs, respectively, wherein the first insulating pads overlap with the first vertical channel structures in a horizontal direction.

公开(公告)号：US20240038493A1

公开(公告)日：2024-02-01

申请号：US18380144

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  Yonghwan KIM ,  Sangwuk PARK ,  Chanhoon PARK ,  Hyuk KIM ,  Edward SUNG

IPC: H01J37/32

CPC classification number: H01J37/32082 ,  H01L21/31144

Abstract: A semiconductor processing apparatus includes an upper electrode and a substrate on a lower electrode disposed inside the process chamber, a first power generator configured to provide a low-frequency signal to the lower electrode, wherein the low-frequency signal varies between a reference voltage and a first voltage at intervals of a first cycle, a second power generator configured to provide a high-frequency signal to the lower electrode, wherein the high-frequency signal has a sinusoidal waveform that oscillates at intervals of a second cycle shorter than the first cycle, and a direct-current (DC) power generator configured to provide a DC bias to the upper electrode. The high-frequency signal is turned off during at least part of a duration for which the low-frequency signal has the first voltage, and the high-frequency signal is turned on and turned off at intervals of a third cycle different from the first and second cycles.

公开(公告)号：US20230317606A1

公开(公告)日：2023-10-05

申请号：US17970008

申请日：2022-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yejeong SEO ,  Hyuk KIM

IPC: H01L23/528 ,  H01L27/108 ,  H01L29/417 ,  H01L29/08 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/41775 ,  H01L29/0847 ,  H01L23/5226

Abstract: A semiconductor device includes an extension structure including a first horizontal conductive line extension, a first interlayer insulating layer, a second horizontal conductive line extension, and a second interlayer insulating layer stacked on a substrate and extending in a first horizontal direction, a first contact configured to pass through the second interlayer insulating layer, the second horizontal conductive line extension, and the first interlayer insulating layer and contact the first horizontal conductive line extension, a second contact configured to pass through the second interlayer insulating layer and contact the second horizontal conductive line extension, and a first contact spacer extending between a sidewall of the first contact and the extension structure and configured to electrically isolate the first contact from the second horizontal conductive line extension.

公开(公告)号：US20160372347A1

公开(公告)日：2016-12-22

申请号：US15008788

申请日：2016-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk KIM ,  Ha-Na KIM ,  Kyoungsub SHIN ,  Jung-Ik OH

IPC: H01L21/67

CPC classification number: H01L21/67253 ,  F16K1/44 ,  F16K51/02 ,  H01L21/67017 ,  H01L21/67126

Abstract: Provided are a substrate processing apparatus capable of performing a semiconductor process using a plasma and a method of forming a semiconductor device using the same. The substrate processing apparatus includes a process chamber, a high vacuum pump, an exhaust flow path between the high vacuum pump and the process chamber, and a vacuum valve in the exhaust flow path. The vacuum valve includes a first valve and a second valve having a smaller orifice than the first valve.

Abstract translation: 提供了能够使用等离子体进行半导体处理的基板处理装置以及使用其形成半导体装置的方法。 基板处理装置包括处理室，高真空泵，高真空泵和处理室之间的排气流路以及排气流路中的真空阀。 真空阀包括具有比第一阀小的孔的第一阀和第二阀。

公开(公告)号：US20250008731A1

公开(公告)日：2025-01-02

申请号：US18392254

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwan CHOI ,  Hyuk KIM ,  Chanju PARK

IPC: H10B43/27

Abstract: A semiconductor device includes a cell array region and a contact region; a gate stack structure groups of gate electrodes; a channel structure extending through the gate stack structure in the cell array region; and gate contact portions connected to respective gate electrodes in the contact region. At least some of the gate contact portions extend through a through gate electrode connected to a connection gate electrode at a lower end portion. The gate contact portions include contact groups extending from a first side to a second side of the gate electrodes in an extending direction. Each of the electrode groups includes an upper group on a lower group. Each of the contact groups includes a first group connected to the upper group and a second group on the second side in the extending direction, and connected to the lower group, and a number of layers of the connection gate electrodes to which the gate contact portions are connected sequentially increases as a distance from a boundary between the first group and the second group increases in the first group and the second group.

公开(公告)号：US20180374961A1

公开(公告)日：2018-12-27

申请号：US15849094

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk KIM ,  Dae Hyun JANG ,  Seung Pil CHUNG ,  Sung Il CHO

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11556 ,  H01L29/10

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

公开(公告)号：US20230066367A1

公开(公告)日：2023-03-02

申请号：US17693328

申请日：2022-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung PARK ,  Hyuk KIM ,  Yeongeun YOOK

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a lower structure including lower wirings. A horizontal wiring layer is disposed on the lower structure while including a horizontal conductive layer, and a horizontal insulating layer extending through the horizontal conductive layer. A stack structure is disposed on the horizontal wiring layer. A channel structure extending into the horizontal wiring layer while extending through the stack structure is provided. A through electrode connected to the lower wirings while extending through the stack structure and the horizontal insulating layer is provided. The stack structure includes insulating layers and electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the insulating layers and the electrode layers. The through electrode includes a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the lower wirings while having a smaller horizontal width than the first portion.

公开(公告)号：US20230065995A1

公开(公告)日：2023-03-02

申请号：US17591949

申请日：2022-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchul SONG ,  Hyuk KIM ,  Sangwuk PARK ,  Jun Haeng LEE ,  Sungil CHO ,  Kaeweon YOU

IPC: G06F16/904

Abstract: A processor-implemented method with data exploration includes: setting first input data and a first target condition; predicting first output data corresponding to the first input data using a first function that models an objective function; and determining second input data using a second function that provides a result of comparison between the first output data and the first target condition.

公开(公告)号：US20200373124A1

公开(公告)日：2020-11-26

申请号：US16706773

申请日：2019-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  Yonghwan KIM ,  Sangwuk PARK ,  Chanhoon PARK ,  Hyuk KIM ,  Edward SUNG

IPC: H01J37/32

Abstract: A semiconductor processing apparatus includes an upper electrode and a substrate on a lower electrode disposed inside the process chamber, a first power generator configured to provide a low-frequency signal to the lower electrode, wherein the low-frequency signal varies between a reference voltage and a first voltage at intervals of a first cycle, a second power generator configured to provide a high-frequency signal to the lower electrode, wherein the high-frequency signal has a sinusoidal waveform that oscillates at intervals of a second cycle shorter than the first cycle, and a direct-current (DC) power generator configured to provide a DC bias to the upper electrode. The high-frequency signal is turned off during at least part of a duration for which the low-frequency signal has the first voltage, and the high-frequency signal is turned on and turned off at intervals of a third cycle different from the first and second cycles.