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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230200055A1

    公开(公告)日：2023-06-22

    申请号：US17874691

    申请日：2022-07-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonghwan KIM ,  Yangdoo KIM ,  Sangwuk PARK ,  Minkyu SUH ,  Sangho LEE ,  Jungpyo HONG

    IPC: H01L27/108 ,  H01L27/12 ,  H01L27/13

    CPC classification number: H01L27/10817 ,  H01L27/1203 ,  H01L27/13 ,  H01L27/10852 ,  H01L27/10823

    Abstract: A semiconductor device including a substrate; storage node contacts on the substrate; lower electrode structures on the storage node contacts; a supporter structure on an external side surface of the lower electrode structures and connecting adjacent lower electrode structures to each other; a dielectric layer on the lower electrode structures and the supporter structure; and an upper electrode structure on the dielectric layer, wherein the lower electrode structures each include a pillar portion in contact with the storage node contacts; and a cylinder portion on the pillar portion, the pillar portion includes a first lower electrode layer having a cylindrical shape and having a lower surface and a side surface; and a first portion covering at least an internal wall of the first lower electrode layer, and the cylinder portion includes a second portion extending from the first portion and covering an upper end of the first lower electrode layer.

    SEMICONDUCTOR PROCESSING APPARATUS
    2.
    发明申请
    SEMICONDUCTOR PROCESSING APPARATUS 审中-公开

    公开(公告)号：US20200373124A1

    公开(公告)日：2020-11-26

    申请号：US16706773

    申请日：2019-12-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junho YOON ,  Yonghwan KIM ,  Sangwuk PARK ,  Chanhoon PARK ,  Hyuk KIM ,  Edward SUNG

    IPC: H01J37/32

    Abstract: A semiconductor processing apparatus includes an upper electrode and a substrate on a lower electrode disposed inside the process chamber, a first power generator configured to provide a low-frequency signal to the lower electrode, wherein the low-frequency signal varies between a reference voltage and a first voltage at intervals of a first cycle, a second power generator configured to provide a high-frequency signal to the lower electrode, wherein the high-frequency signal has a sinusoidal waveform that oscillates at intervals of a second cycle shorter than the first cycle, and a direct-current (DC) power generator configured to provide a DC bias to the upper electrode. The high-frequency signal is turned off during at least part of a duration for which the low-frequency signal has the first voltage, and the high-frequency signal is turned on and turned off at intervals of a third cycle different from the first and second cycles.

    METHODS OF FORMING SEMICONDUCTOR DEVICES
    6.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230110190A1

    公开(公告)日：2023-04-13

    申请号：US17938684

    申请日：2022-10-07

    Applicant: Samsung Electronics Co., Ltd

    Inventor： JINYOUNG PARK ,  Jungpyo HONG ,  Yangdoo KIM ,  Yonghwan KIM ,  Sangwuk PARK

    IPC: H01L21/033 ,  H01L21/308 ,  H01L21/027

    Abstract: Methods of forming a semiconductor device may include: providing a substrate on which a layer is formed; forming a lower hard-mask layer, which includes silicon, on the layer; forming an upper hard-mask pattern, which includes oxide, on the lower hard-mask layer; forming a lower hard-mask pattern by etching the lower hard-mask layer using the upper hard-mask pattern as an etch mask and using an etching gas that includes a metal-chloride-based first gas and a nitride-based second gas; and forming a plurality of contact holes in the layer by etching the material layer using the lower hard-mask pattern as an etch mask.

    SEMICONDUCTOR PROCESSING APPARATUS
    8.
    发明公开
    SEMICONDUCTOR PROCESSING APPARATUS 审中-公开

    公开(公告)号：US20240038493A1

    公开(公告)日：2024-02-01

    申请号：US18380144

    申请日：2023-10-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junho YOON ,  Yonghwan KIM ,  Sangwuk PARK ,  Chanhoon PARK ,  Hyuk KIM ,  Edward SUNG

    IPC: H01J37/32

    CPC classification number: H01J37/32082 ,  H01L21/31144

    Abstract: A semiconductor processing apparatus includes an upper electrode and a substrate on a lower electrode disposed inside the process chamber, a first power generator configured to provide a low-frequency signal to the lower electrode, wherein the low-frequency signal varies between a reference voltage and a first voltage at intervals of a first cycle, a second power generator configured to provide a high-frequency signal to the lower electrode, wherein the high-frequency signal has a sinusoidal waveform that oscillates at intervals of a second cycle shorter than the first cycle, and a direct-current (DC) power generator configured to provide a DC bias to the upper electrode. The high-frequency signal is turned off during at least part of a duration for which the low-frequency signal has the first voltage, and the high-frequency signal is turned on and turned off at intervals of a third cycle different from the first and second cycles.

    METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE
    9.
    发明公开
    METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20230320061A1

    公开(公告)日：2023-10-05

    申请号：US17979069

    申请日：2022-11-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minkyu SUH ,  Yangdoo KIM ,  Yonghwan KIM ,  Sangwuk PARK ,  Geonyeop LEE ,  Dokeun LEE ,  Jungpyo HONG

    IPC: H01L27/108

    CPC classification number: H01L27/1085

    Abstract: A method of manufacturing an integrated circuit device includes forming a mold structure, which has a mold layer and a support layer sequentially stacked, on a substrate, forming a vertical hole through the mold structure in a vertical direction and a bowing space extending outward from the vertical hole in a horizontal direction in a first vertical level area, exposing the vertical hole and the bowing space to a preprocessing atmosphere to make the support layer have a first surface state and the mold layer have a second surface state different from the first surface state, forming a bowing complementary pattern filling the bowing space by a selective deposition process using the difference between the first surface state and the second surface state, and forming a lower electrode in the vertical hole and in contact with the mold layer, the support layer, and the bowing complementary pattern.

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