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    Efficient generalized tensor product codes encoding schemes
    2.
    发明授权
    Efficient generalized tensor product codes encoding schemes 有权

    公开(公告)号：US10333554B2

    公开(公告)日：2019-06-25

    申请号：US15639475

    申请日：2017-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Moshe Ben Ari ,  Avner Dor ,  Elona Erez ,  Jun Jin Kong ,  Yaron Shany

    IPC: H03M13/00 ,  H03M13/15 ,  H03M13/29

    Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=Ũ·s.

    Mapping bits to memory cells using sector spreading
    3.
    发明授权
    Mapping bits to memory cells using sector spreading 有权

    公开(公告)号：US10262728B2

    公开(公告)日：2019-04-16

    申请号：US15288443

    申请日：2016-10-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Iddo Naiss ,  Noam Livne ,  Elona Erez ,  Jun Jin Kong

    IPC: G06F11/10 ,  G11C11/56 ,  G11C29/52 ,  G11C29/00

    Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.

    Nonvolatile memory devices and methods of controlling the same
    4.
    发明授权
    Nonvolatile memory devices and methods of controlling the same 有权

    公开(公告)号：US10606760B2

    公开(公告)日：2020-03-31

    申请号：US15684252

    申请日：2017-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Elona Erez ,  Avner Dor ,  Moshe Twitto ,  Jun Jin Kong

    IPC: G06F12/1009 ,  G06F12/02

    Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

    Nonvolatile memory devices and methods of controlling the same
    5.
    发明授权
    Nonvolatile memory devices and methods of controlling the same 有权

    公开(公告)号：US10289561B2

    公开(公告)日：2019-05-14

    申请号：US15671855

    申请日：2017-08-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Elona Erez ,  Avner Dor ,  Jun-Jin Kong

    IPC: G06F12/10 ,  G06F12/1009 ,  G06F3/06

    Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

    Nonvolatile memory devices and methods of controlling the same
    6.
    发明授权
    Nonvolatile memory devices and methods of controlling the same 有权
    非易失存储器件及其控制方法

    公开(公告)号：US09483413B2

    公开(公告)日：2016-11-01

    申请号：US14523159

    申请日：2014-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Avner Dor ,  Elona Erez ,  Shay Landis ,  Jun Jin Kong

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7203

    Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

    Abstract translation: 至少一个示例性实施例公开了一种控制包括多个块的非易失性存储器件的方法，每个块包括多个物理页。 该方法包括分别接收与第一多个逻辑地址相关联的多个逻辑页面，并根据第一多个逻辑页面的逻辑地址的升序将多个逻辑页面写入多个物理地址。

    Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID)
    8.
    发明授权
    Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID) 有权

    公开(公告)号：US10387254B2

    公开(公告)日：2019-08-20

    申请号：US15730943

    申请日：2017-10-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Yaron Shany ,  Avner Dor ,  Elona Erez ,  Jun Jin Kong

    IPC: G06F11/10 ,  G06F3/06 ,  H03M13/15 ,  H03M13/29

    Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n−{tilde over (k)}j, where the first n-kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix R, of dimension (n−{tilde over (k)}j)(n−{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n−kl columns Tj and has k1−{tilde over (k)}j columns; finding a vector c−(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n−{tilde over (k)}j; and solving ( A | I ) ⁢ ( a b ) = ( Q j | T j ) ⁢ s ~ = T j ⁢ s ⁢ ⁢ where ⁢ ⁢ a = 0 ⁢ ⁢ and ⁢ ⁢ b = T j ⁢ s , where a=0 and b=Tjs, and codeword c is nonzero only on the last n−{tilde over (k)}j=n−kj bits.

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