Half-match deduplication
    1.
    发明授权

    公开(公告)号:US10860233B2

    公开(公告)日:2020-12-08

    申请号:US16382374

    申请日:2019-04-12

    Abstract: A memory system may include a memory device configured to store data received from a host; and a memory controller configured to, receive a received block of the data and a logical address associated with the data from the host, detect at least one halves of the received block as being duplicate halves based on whether a respective one of the at least one halves of the received block match one or more existing halves of stored blocks stored in the memory device, selectively store the at least one halves of the received block in the memory device based on whether the respective one of the at least one halves are duplicate halves such that the duplicate halves of the received block are not stored in the memory device, and store metadata associated with retrieving the received block.

    Consolidation of copy-back and write in PRAM blocks

    公开(公告)号:US10783970B2

    公开(公告)日:2020-09-22

    申请号:US16218210

    申请日:2018-12-12

    Abstract: A method for performing a write operation in a random access memory (RAM) includes selecting a target block in a RAM with a greatest number of invalid pages, reading valid pages from target block, when a number of invalid pages is greater than a predetermined threshold, performing a bitline-wise block erase of the target block in said RAM, and copying-back valid data to the erased target block in a row-by-row set operation, wherein the erased target block is written with the valid data. Performing the bitline-wise block erase includes sequentially powering on each bitline with a predetermined reset voltage where all other bitlines and wordlines are grounded.

    Mapping bits to memory cells using sector spreading

    公开(公告)号:US10262728B2

    公开(公告)日:2019-04-16

    申请号:US15288443

    申请日:2016-10-07

    Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.

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