公开(公告)号：US20140219000A1

公开(公告)日：2014-08-07

申请号：US14107199

申请日：2013-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi-Sung OH ,  Chul-Sung PARK ,  Nak-Won HEO ,  Dong-Hyun SOHN

IPC: G11C17/16 ,  G11C29/52 ,  G06F12/14

CPC classification number: G11C17/16 ,  G06F12/1433 ,  G06F2212/2142 ,  G11C7/24 ,  G11C17/18 ,  G11C29/785 ,  G11C2029/4402

Abstract: A method of programming a memory device including a one-time programmable (OTP) cell array configured to include at least one of a protected area and a programmable area are disclosed. The method includes receiving a fuse-program command to initiate a fuse-programming operation; checking whether the programmable area exists in the OTP cell array, terminating the fuse-programming operation when the OTP cell array does not include the programmable area, performing a fuse-programming operation on the programmable area when the OTP cell array includes the programmable area thereby programming fuses to create a fuse-programmed area; setting the fuse-programmed area of the OTP cell array as the protected area.

Abstract translation: 公开了一种编程包括被配置为包括保护区域和可编程区域中的至少一个的一次可编程（OTP）单元阵列的存储器件的方法。 该方法包括接收熔丝编程命令以启动熔丝编程操作; 检查OTP单元阵列中是否存在可编程区域，当OTP单元阵列不包括可编程区域时终止熔丝编程操作，当OTP单元阵列包括可编程区域时在可编程区域上执行熔丝编程操作，从而 编程保险丝创建熔丝编程区域; 将OTP单元阵列的熔丝编程区域设置为保护区域。

公开(公告)号：US20130329478A1

公开(公告)日：2013-12-12

申请号：US13937367

申请日：2013-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo Yu ,  Sang-Bo LEE ,  Hong-Sun HWANG ,  Dong-Hyun SOHN

IPC: G11C5/02 ,  G11C7/22

CPC classification number: G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract translation: 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

公开(公告)号：US20130237019A1

公开(公告)日：2013-09-12

申请号：US13864437

申请日：2013-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Woo PARK ,  Hong-Sun HWANG ,  In-Gyu BAEK ,  Dong-Hyun SOHN

IPC: H01L21/77

CPC classification number: H01L21/77 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/24

Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

Abstract translation: 叠层半导体存储器件包括具有功能电路，多个存储单元阵列层以及至少一个连接层的半导体衬底。 存储单元阵列层堆叠在半导体衬底之上。 连接层堆叠在半导体衬底之上，独立于存储单元阵列层。 连接层将布置在存储单元阵列层上的存储单元选择线电连接到功能电路。