公开(公告)号：US20140331006A1

公开(公告)日：2014-11-06

申请号：US14208339

申请日：2014-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-Ju CHUNG ,  Chul-Sung PARK ,  Tae-Seong JANG ,  Gong-Heum HAN ,  Jang-Woo RYU

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1009

Abstract: A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.

Abstract translation: 半导体存储器件包括存储单元阵列，数据反转/掩模接口和写入电路。 数据反转/掩模接口接收包括多个单元数据的数据块，多个单元数据中的每一个具有第一数据大小，并且数据反转/掩码接口选择性地启用与多个单元数据中的每一个相关联的每个数据掩码信号 基于每个单位数据的第二数据大小中的第一数据位的数量的单元数据。 第二数据大小小于单位数据的第一数据大小。 写入电路接收数据块并执行屏蔽写入操作，其响应于数据屏蔽信号选择性地将多个单元数据中的每一个写入存储单元阵列。

公开(公告)号：US20140219000A1

公开(公告)日：2014-08-07

申请号：US14107199

申请日：2013-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi-Sung OH ,  Chul-Sung PARK ,  Nak-Won HEO ,  Dong-Hyun SOHN

IPC: G11C17/16 ,  G11C29/52 ,  G06F12/14

CPC classification number: G11C17/16 ,  G06F12/1433 ,  G06F2212/2142 ,  G11C7/24 ,  G11C17/18 ,  G11C29/785 ,  G11C2029/4402

Abstract: A method of programming a memory device including a one-time programmable (OTP) cell array configured to include at least one of a protected area and a programmable area are disclosed. The method includes receiving a fuse-program command to initiate a fuse-programming operation; checking whether the programmable area exists in the OTP cell array, terminating the fuse-programming operation when the OTP cell array does not include the programmable area, performing a fuse-programming operation on the programmable area when the OTP cell array includes the programmable area thereby programming fuses to create a fuse-programmed area; setting the fuse-programmed area of the OTP cell array as the protected area.

Abstract translation: 公开了一种编程包括被配置为包括保护区域和可编程区域中的至少一个的一次可编程（OTP）单元阵列的存储器件的方法。 该方法包括接收熔丝编程命令以启动熔丝编程操作; 检查OTP单元阵列中是否存在可编程区域，当OTP单元阵列不包括可编程区域时终止熔丝编程操作，当OTP单元阵列包括可编程区域时在可编程区域上执行熔丝编程操作，从而 编程保险丝创建熔丝编程区域; 将OTP单元阵列的熔丝编程区域设置为保护区域。

公开(公告)号：US20140198596A1

公开(公告)日：2014-07-17

申请号：US14139736

申请日：2013-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun SEO ,  Chul-Sung PARK ,  Young-Dae LEE

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may also include: a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode.

Abstract translation: 提供了半导体存储器件的位线读出放大器源节点控制电路。 感测放大器源节点控制电路可以包括连接在读出放大器的源节点和读出放大器驱动信号线之间的源极驱动器，用于将读出放大器的源极节点驱动到设定的电压电平。 感测放大器源节点控制电路还可以包括：用于在设定的工作模式下浮置读出放大器驱动信号线的浮置电路; 以及与感测放大器的源极节点和感测放大器驱动信号线之间的源极驱动器并联连接的控制器，用于在设定的工作模式下控制读出放大器驱动信号线的电平。