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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250081599A1

    公开(公告)日：2025-03-06

    申请号：US18616279

    申请日：2024-03-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong Hoon HWANG ,  Hyo Jin KIM ,  Byung Ho MOON ,  Kyoung-MI PARK ,  Kyung Hee CHO

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    Abstract: A semiconductor device that includes a lower pattern extending in a first direction, a first channel pattern on the lower pattern, and includes a plurality of first sheet patterns, a second channel pattern on the lower pattern, includes a plurality of second sheet patterns and spaced apart from the first channel pattern, a first gate structure which extends around the first sheet pattern, and includes a first gate electrode and a first gate insulating film, a second gate structure which extends around the second sheet pattern, and includes a second gate electrode and a second gate insulating film, a first gate capping pattern and a second gate capping pattern. The number of first sheet patterns is different from the number of second sheet patterns, and a thickness of the first gate capping pattern is different from a thickness of the second gate capping pattern.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250132257A1

    公开(公告)日：2025-04-24

    申请号：US18650306

    申请日：2024-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyo Jin KIM ,  Dong Hoon HWANG ,  Min Chan GWAK

    IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

    Abstract: A semiconductor device may include a via pattern connected to a conductive pattern on a substrate, the via pattern including a lower via pattern and an upper via pattern stacked on the lower via pattern, and a wiring line connected to the upper via pattern and extending in a second direction. The wiring line may include a same metal as the upper via pattern. A bottom width of the wiring line may be greater than a top width of the wiring line. a widths of an upper face of the lower via pattern may be equal to width of the bottom face of the upper via pattern.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20250040215A1

    公开(公告)日：2025-01-30

    申请号：US18439634

    申请日：2024-02-12

    Applicant: SAMSUNG ELECTRONICS CO, LTD.

    Inventor： Dong Hoon HWANG ,  Hyo Jin KIM ,  Myung II KANG ,  Tae Hyun RYU ,  Kyu Nam PARK ,  Woo Seok PARK

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes a lower pattern. A channel isolation structure and a field insulating layer contact the lower pattern. A gate structure is on the lower pattern, in contact with the channel isolation structure. A channel pattern is on the lower pattern, and includes sheet patterns, each being in contact with the channel isolation structure. A source/drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source/drain pattern. The second region of the channel isolation structure includes portions whose widths increase as a distance from a bottom surface of the field insulating layer increases. A width of an uppermost portion of the channel isolation structure is greater than a width of a lowermost portion of the channel isolation structure

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240047463A1

    公开(公告)日：2024-02-08

    申请号：US18131548

    申请日：2023-04-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong Hoon HWANG ,  Seung Min SONG ,  Min Chan GWAK

    IPC: H01L27/12 ,  H01L21/84

    CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L21/823481

    Abstract: In some embodiments, a semiconductor device includes a first active pattern extended in a first horizontal direction on a substrate, a second active pattern extended in the first horizontal direction on the substrate, a first bottom gate electrode extended in a second horizontal direction on the first active pattern, a first upper gate electrode extended in the second horizontal direction on the first bottom gate electrode, a second bottom gate electrode extended in the second horizontal direction on the second active pattern, a second upper gate electrode extended in the second horizontal direction on the second bottom gate electrode, and a first gate cut comprising a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode. A width of the second portion exceeds a width of the first portion.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250159929A1

    公开(公告)日：2025-05-15

    申请号：US18756943

    申请日：2024-06-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoung-Mi PARK ,  Hyo Jin KIM ,  Dong Hoon HWANG ,  Young Jin YANG ,  Kyung Hee CHO

    IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device is provided. The semiconductor device includes a first lower pattern extending in a first direction and including first and second sidewalls, which are opposite to each other in a second direction, and upper and lower surfaces, which are opposite to each other in a third direction, a channel separation structure extending in the first direction and contacting the first sidewall of the first lower pattern, a field insulating film contacting the second sidewall of the first lower pattern, first channel patterns disposed on an upper surface of the first lower pattern and including first sheet patterns, which are spaced apart from one another in the third direction, the first sheet patterns contacting the channel separation structure, first source/drain patterns contacting the first channel patterns and the channel separation structure, contact blocking patterns disposed on the first source/drain patterns and formed of an insulating material, the contact blocking patterns having upper surfaces on the same plane as an upper surface of the channel separation structure, first backside source/drain contacts disposed within the first lower pattern and connected to the first source/drain patterns and backside wiring lines disposed on the lower surface of the first lower pattern and connected to the first backside source/drain contacts.

    SEMICONDUCTOR DEVICE
    8.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240145560A1

    公开(公告)日：2024-05-02

    申请号：US18211786

    申请日：2023-06-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong Hoon HWANG ,  Myung Il KANG ,  Do Young CHOI

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device includes an active pattern on a substrate extending in a first horizontal direction, a gate electrode on the active pattern extending in a second horizontal direction, a source/drain region on the active pattern, an upper source/drain region apart from the lower source/drain region, a lower source/drain between upper and lower source/drain regions and connected to the lower source/drain region, an upper source/drain connected to an upper source/drain region, an interlayer insulating layer surrounding the upper source/drain region, a through-via on opposing sidewalls in the second horizontal direction extending through the interlayer insulating layer in the vertical direction, the through-via being spaced from the upper source/drain region and upper source/drain contact in the second horizontal direction, the through-via being connected to the lower source/drain contact, and a dam structure on each of the opposing sidewalls in the horizontal direction of the upper source/drain region.

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